Programme to enhance reconfigurable technology

Edited by the Electronicstalk editorial team Oct 7, 2004

IMEC and Freescale Semiconductor are working together on reconfigurable multiprocessor systems.

IMEC and Freescale Semiconductor are working together on reconfigurable multiprocessor systems.

By joining IMEC's Industrial Affiliation Programme (IIAP), Freescale plans to deliver leading edge mobile multimedia solutions by using IMEC's existing and future reconfigurable technology, capitalising on IMEC's total system approach and its focus on low power, as well as leveraging IMEC's system design tools and methodologies.

This co-operation promises to enable Freescale to establish its own proprietary seamless mobility platform.

Reconfigurable data flow is needed to provide the performance and flexibility required in future seamless mobility products.

IMEC's solution is characterised by a complete system, low-power approach.

"The combination of Freescale's microprocessor knowhow and insight into requirements of embedded systems applications, combined with IMEC's expertise in reconfigurable architectures and system design, makes this collaboration a win-win endeavour", said Rudy Lauwereins, Vice-President of Design Technology for Integrated Information and Communication Systems at IMEC.

"IMEC's technology will complement Freescale's long-standing technology position in wireless SoC design and provide our customers with innovative and disruptive semiconductor solutions", said Ken Hansen, Senior Technical Fellow and Director of Advanced Technology for Freescale's Wireless Group.

"By working together, this vision of seamless mobility may be a reality earlier than originally anticipated".

The architecture is based on IMEC's novel processor architecture template, which combines VLIW (very-long instruction word) processors and coarse-grain reconfigurable hardware.

The combination of these two highly parallel processor architectures complemented with adequate memory architecture, provides an ultra-low-power ASIP (application-specific instruction set processor) with increased flexibility and performance.

Together with the architecture template, a C compiler is developed which provides efficient mapping of applications allowing a fast design cycle while keeping the performance breakthrough delivered by the new architecture.