Programme focuses on system-level integration

IMEC will bring electronic design automation providers and integrated device manufacturers together in its new industrial affiliation programme on system-level integration.

IMEC will bring electronic design automation (EDA) providers and integrated device manufacturers (IDMs) together in its new industrial affiliation programme on system-level integration.

Working together through IMEC, the two industry segments will develop solutions for the increasing number of design-for-manufacturing (DFM) problems.

As semiconductor technology scaling drops to sub-90nm nodes, the number of technology barriers increases, with only marginal process technology improvements possible.

Increasing interconnect delays lead to timing closure problems.

Power consumption increases significantly because of thermal heating, exploding static power consumption and increasing energy in the interconnects.

These factors make it extremely difficult, or even impossible, to design power-aware systems and applications.

At the same time, manufacturing tolerances in process technology are not scaling at the same pace as the physical gate length of the transistor.

This situation increases the variability in device characteristics but also narrows the operating window for correct functioning of individual circuits.

This has a negative impact on chip yield.

Besides the static variability caused by increasing device mismatch, dynamic variability of device characteristics caused by thermal effects at run-time further narrows the operating window of the circuits.

Through its industrial affiliation programme (IIAP) on system-level integration (SLI), IMEC will establish a methodology and supporting techniques and tools to improve the design of robust and better performing ICs despite the limitations of future process technology nodes.

The main performance metrics to be addressed are energy, delay and area of the IC.

The methodology will be used for the design of low-power ICs typically used for wireless and multimedia applications.

Because advanced wireless and multimedia systems are largely data dominated, memories account for a dominant fraction both in energy and in area.

Therefore, the programme will focus on providing adequate system design methods and tools for exploring and optimising memory architectures, memory organisation, and memory interconnection network of the SoC.

A framework will be built allowing researchers to concurrently explore the impact of technology scaling and static and dynamic variability on circuit and system performance for various system architectures.

IMEC has joined forces with the digital circuit design team of the ESAT-MICAS laboratory of the KU Leuven to model deep-submicron technology effects on circuit behaviour and to develop circuit techniques to overcome some of these effects.

The models will be exploited to explore various architectures trading power, speed and chip area in the most optimal way.

The process variability impact will be tackled at three levels: at technology level by layout corrections; at circuit level by novel monitor and control circuitry to stabilise the correct functioning of functional blocks; and at system level by providing a run-time controller that minimises impact of the variability of the individual system components.

The system-level optimisation will be done in close collaboration with the circuit- and technology-level optimisation by interpreting the monitor signals and steering the control circuitry in a proper way.

The programme output offers valuable information for EDA providers and IC device manufactures to identify the main technology limitations and how to deal with these limitations by novel design solutions.

It also offers to the semiconductor equipment community the means to benchmark the potential of an improvement in manufacturing tolerance on device variability and subsequent circuit and system performance.

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