Centre focuses on packaging and system integration

IMEC's new advanced packaging and interconnect centre brings together a number of competences to tackle the challenges in future technologies for packaging and system integration.

IMEC has opened its advanced packaging and interconnect centre, APIC, which is committed to play a central role in bringing together the different players in the IC food chain around joint research programmes for future packaging and system-integration technologies.

The centre's focus lies in bridging the "interconnect gap" between circuit and system, heterogeneous integration of RF components and thermal management in high-power density devices.

IMEC's advanced packaging and interconnect centre brings together a number of competences to tackle the challenges in future technologies for packaging and system integration.

APIC offers solutions that are vertically and horizontally elaborated: vertically in terms of technologies that range from the circuit up to the system level; and horizontally because each level is supported by experienced teams in design, processing, analysis and reliability.

This broad range of competences within APIC feeds a number of well-defined research programmes.

Each has an IC-centric approach and is driven by the semiconductor technology roadmap and by miniaturisation of electronic systems; in particular those needed for ambient intelligence applications.

APIC begins with the launch of two programmes: 3D-stacked IC (3D-SIC) and 3D systems-on-chip (3D-SoC).

The 3D-SIC programme is also part of IMEC's industrial affiliation programme (IIAP) on "advanced interconnect solutions for future technology nodes".

The IIAP aims at finding solutions for interconnect technologies for the 45 and 32nm node and below.

Until now, main focus lay on the use of Cu and low-k materials in future scaled interconnect modules.

Based on promising results from a benchmarking study comparing power and performance metrics of scaled and unscaled global Cu/low-k wires, optical interconnects, LC interconnects and 3D-stacked ICs, IMEC decided to include this 3D-SIC research in the advanced-interconnect IIAP.

The 3D-stacked ICs - characterised by short high-density interconnects between stacked chips, at the transistor level - showed several advantages concerning power and performance, and the ability to interconnect chips with divergent process flows.

The 3D Si through connections are realised during the IC foundry process, between the front-end and back-end of line.

The 3D-SoC programme will develop a platform for heterogeneous integration of SoCs.

3D-SoCs are systems in which circuit blocks ("tiles") on a die are interconnected to circuit blocks on another die after passivation, without passing through the regular chip I/O pads.

Each of these dice may be realised using a different technology.

This programme aims to realise 3D connections after the Si foundry process (post-passivation), using wafer-level-packaging (WLP) technologies.

The target dimensions of the through Si connections are diameters down to approximately 25um and pitches down to approximately 50um, for wafers thinned down to 200 to 50um.

The realisation of reliable, low-resistance, low-capacitance and low-cost through-wafer interconnects is a major target for the IMEC's 3D-SoC technology development.

Special attention is given to through Si via reliability and RF through applications.

Within all APIC programmes activities are aimed at prototyping, characterisation and reliability testing.

Manufacturability and low-cost processing are key elements along the way.

Other programmes will be defined around heterogeneous integration, wafer-level packaging and thermal management.

APIC currently groups more than 30 partners worldwide including integrated device manufacturers (IDMs), system houses, packaging, assembly and test houses, equipment and material suppliers and fabless companies.

The programmes are based on IMEC's expertise in joint research and development, which guarantees a professional approach for sharing of costs, risks and talent.

Most of the results will be co-owned, although there is room for a limited amount of proprietary results.

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