Profiling technique opens up nitride-based memory

A new profiling technique for the accurate extraction of charge profiles in nitride-based memory has allowed for the optimisation of write/erase voltages using a novel operating mode.

IMEC and Infineon Technologies have developed a profiling technique for the accurate extraction of charge profiles in nitride-based memory, and this has allowed for the optimisation of write/erase voltages using a novel operating mode.

This may overcome the major reliability problems of nitride-based memory, which hampered its competitiveness in the nonvolatile Flash market.

Recently, nitride memory has regained a lot of interest because of its process simplicity and the highly localised charge trapping mechanism in nanoscale material defects.

The latter could turn out to be more scalable than the conventional floating gate approach widely used in Flash memories today.

However, this dual bit storage requires hot holes for erasing, resulting in accumulation of residual charges with increasing numbers of write/erase cycles.

This leads to new reliability issues - memory window walk-out (unstable threshold voltage) and degradation of the retention after cycling (RAC) - which delay the further dissemination of nitride technology into the wide variety of Flash application areas.

As a consequence, the local charge storage concept is only competitive within a small segment of the Flash market today.

IMEC and Infineon have now realised a new profiling technique which will enable companies to fully exploit their nitride technologies.

The breakthrough will allow nitride technology to compete with (conventional) Flash in its full application area of both stand-alone code and data storage Flash, as well as in the embedded arena (including automotive applications).

The new profiling technique allows - for the first time - the accurate and independent extraction of both electron and hole distributions.

Based on this technique, write and erase operations have been optimised and a new operating mode has been found which leads to 100% matching of the carrier profiles.

In case of complete matching after one write/erase cycle (ie the injected holes exactly compensate for the first injected electrons), the window walk-out effect disappears completely resulting in a stable threshold voltage.

Also, retention after cycling remains identical to the retention of a fresh device.

These results open perspectives for both high cycle applications (1 million cycles have been demonstrated) as well as for high retention applications (such as stand-alone code storage and automotive microcontrollers).

Additional benefits of the technique are the smaller periphery (because verify may be skipped and erase voltage is lower) and the sharper distributions, which allow for further channel length scaling.

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