Research addresses sub-45nm analogue challenges

A new industrial affiliation programme on analogue/RF CMOS for the 45nm era aims to keep conquering the challenges of the international technology roadmap for semiconductors.

The new IMEC industrial affiliation programme (IIAP) on analogue/RF CMOS for the 45nm era aims to keep conquering the challenges of the international technology roadmap for semiconductors.

The programme aims to develop process modules and device architectures to achieve RF CMOS performance at the 45nm node and to provide the necessary models for active and passive devices.

The potential of the technology will be assessed through the benchmarking of circuit demonstrators.

To maintain a competitive position in the analogue/RF domain, significant efforts are needed for a timely exploration and exploitation of analogue/RF applications that will become available in future CMOS technology.

Until now, there is no worldwide consensus for sub-45nm mixed signal technologies.

An early assessment of the potential technologies for analogue/RF CMOS applications is therefore mandatory to establish a long-term development strategy.

To this end, IMEC has launched a new IIAP, 45nm analogue/RF CMOS, that strongly builds on the successful results of the preceding 90nm programme.

The continued scaling opens perspectives for CMOS well beyond the 10GHz frequency range.

The scaling will also allow for further reduction of power consumption for applications in the 1-10GHz range.

However, at the same time, limitations start to appear, especially with respect to Vdd scaling and loss of analogue performance with the introduction of new materials.

Also, the 45nm node (and beyond) is not well established for digital CMOS, which makes it more difficult to assess the analogue/RF performance on the level of basic building blocks.

The analogue/RF-CMOS IIAP has started with an early assessment of the analogue and RF performance of the different advanced process modules and device architectures.

As a first result, a comparative study of planar MOSFETs versus FinFETs will be presented at the IEDM conference in Washington at the end of this year.

The second objective of the IIAP is to develop circuit topologies for 45nm analogue/RF CMOS that cope with the low Vdd operation and possible degradations of analogue performance, with very high operating frequencies or with ultralow power consumption.

The third objective is to provide circuit designers with state-of-the-art models of active and passive components for the 45nm analogue/RF CMOS.

The IIAP builds on IMEC's multidisciplinary expertise in silicon process technology, packaging technology with focus on the integration of passive components and circuit design.

The IIAP will run over 3 years.

IMEC is in the process of recruiting additional partners for its new IIAP.

Besides the traditional candidates such as IDMs, equipment and material suppliers, fabless companies are also invited to participate.

Back to top