CMOS courses suit management and engineers

Plasma Etching for CMOS Technology and ULSI Applications explains the performance and limitations of plasma processes for CMOS applications and ULSI.

IMEC is offering two and three-day courses directed at engineers and technicians, managers and executives with responsibility for process development and support, process integration and device design as well as chip manufacturing, metrology and materials research, marketing and sales.

The courses are held during May and June 2008 and taught by researchers at IMEC's facilities in Leuven.

Plasma Etching for CMOS Technology and ULSI Applications (13th to 15th May) is directed at engineers and technicians as well as other industry officials who need a deeper understanding of the performance and limitations of plasma processes for CMOS applications and ULSI.

It covers fundamental and practical aspects of front-end and back-end processes for deep submicron CMOS.

The emphasis is on real-world problems in manufacturing, integration and device scaling.

Day 1 covers the fundamentals, including passivation layers, etch mechanisms in halogen-based plasmas, mass spectrometry analyses, monitoring chamber walls coating and micro-trenching.

Day 2 handles gate etching strategy and chemistry, Si mask material, thin-gate oxide behaviour, resist trimming, dual-doped gates, soft landing steps, metal gate etching, high-k etching, shallow-trench isolation and passivation layers on STI sidewalls.

Day 3 deals with oxide and low-k etching, fluorocarbon film thickness measurement, dual hard mask strategies and the impact of ashing plasmas and chemistries on low-k material modifications.

The two-day course on SOI technologies for analogue, digital and RF SOCs and microsystems applications (15th and 16th May) addresses advanced SOI issues in low-voltage, low-power CMOS systems on chip, with an emphasis on analogue and microwave functions, from basic technology and device levels to original circuit studies.

It covers processes from submicron CMOS for pure analogue to advanced multiple-gate deca-nanometre CMOS for systems-on-chip.

Day 2 will examine bulk and surface micro-machined SOI MEMS and report on recent SOI developments of thin three-dimensional (3D) released micro-sensors and thin di-electric membranes, as well as micro-machines implementing new experimental tools to probe mechanical responses at very small scales.

Silicon processing for sub-90nm circuit fabrication (11th to 13th June) targets engineers, managers and executives in process development, support and integration, device design and manufacturing, materials, marketing and sales.

It is a training programme focusing on deep sub-micron devices.

Day 2 will be dedicated to business managers' approaches to design flow, high-level specification, system design, synthesis, verification, timing closure, layout generation, cell libraries, IP blocks, verification, test pattern generation, GDSII-layers, reticles, alignment, defect density, yield and cost.

CMOS scaling problems pertinent to the 90nm node are discussed and an outlook towards 45nm and lower is given.

The course covers a methodology for yielding products and ramping up production while considering the power-performance trade-off as a fundamental limiter.

Day 3 covers contact metallisation and metal CMP, advances in on-chip interconnect, damascene and low-k, as well as key process integration and manufacturing.

Mass-produced multiGbit Flash memory in 56nm technology is also covered, including an overview of basic mechanisms.

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