Product category:
Intellectual Property Cores
News Release from: Impinj | Subject: Aeon/MTP memory
Edited by the Electronicstalk Editorial
Team on 27 September 2007
Process breakthrough for memory IP
Multiple-time programmable memory designed with 2.5V floating-gate transistors has been verified on TSMC's 65nm LP process.
Nonvolatile memory IP specialist Impinj has verified its multiple-time programmable Aeon/MTP memory designed with 2.5V floating-gate transistors on TSMC's 65nm LP process A semiconductor technology breakthrough that leverages Impinj's extensive semiconductor design expertise and TSMC's advanced manufacturing capability, Aeon/MTP is the first available NVM IP based on floating gate technology with 2.5V transistors
This article was originally published on Electronicstalk on 25 Apr 2007 at 8.00am (UK)
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Impinj is also developing Aeon/MTP NVM cores in TSMC's 45nm processes to address escalating demand from leading-edge SoC designers for logic NVM in industry-leading process geometries.
Embedded in more than 600 million chips from leading semiconductor companies, Aeon/MTP cores allow many more IC designs to leverage the benefits of multiple-time programmable (MTP) NVM in standard logic CMOS processes.
Multiple-time programmable NVM provides significant SoC design flexibility and testability advantages over one-time programmable NVM, including security key refresh capability, in-field user data configuration and in-field performance optimisation.
The 65nm Aeon/MTP product: is available in 32bit to 8Kbit configurations for maximum design flexibility; offers 15,000-write-cycle endurance for frequent in-field updating or reprogramming; provides 10-year data retention for long product life; and features a -40 to +125C operating temperature envelope for high-demand industrial applications.
"The availability of Aeon/MTP in 65nm processes dispels a long-held industry misconception that floating gates manufactured in 2.5V processes do not retain charge", says Larry Morrell, Vice President and General Manager of IP Products at Impinj.
"Aeon/MTP NVM with 2.5V floating gate transistors has been put through rigorous testing and its reliability and performance have been proven".
Impinj's Aeon/MTP cores in TSMC's 65nm process will be available in November to qualified customers with broad availability in the first quarter of 2008.
Development of Aeon/MTP cores in TSMC's 45nm process is under way, with planned availability in late 2008.
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