Product category:
Design and Development Software
News Release from: Impulse Accelerated Technologies | Subject: CoDeveloper Pro
Edited by the Electronicstalk Editorial
Team on 07 October 2004
Tools explore FPGA optimisation
strategies
Impulse Accelerated Technologies today announced the release of its CoDeveloper Pro optimisation and debugging software.
Impulse Accelerated Technologies today announced the release of its CoDeveloper Pro optimisation and debugging software Offered as a complement to the CoDeveloper C-to-FPGA compiler, the Pro tools add new optimisation and cycle-accurate debugging capabilities to improve quality-of-results for FPGA-based software/hardware acceleration
This article was originally published on Electronicstalk on 10 Oct 2005 at 8.00am (UK)
Related stories
Software optimises C-based FPGA designs
Impulse Accelerated Technologies has released its CoDeveloper Pro optimisation and debugging software to complement its CoDeveloper C-to-FPGA compiler.
Software adds C-based FPGA design input
CoDeveloper C-to-FPGA tools from Impulse Accelerated Technologies can now be integrated with advanced FPGA synthesis and verification tools from Synplicity.
According to David Pellerin, Chief Technology Officer at Impulse: "CoDeveloper Pro allows C programmers have immediate, interactive feedback on their software-to-hardware programming choices, and to quickly test different C coding styles and optimisation selections".
"These tools, when combined with the CoDeveloper C-to-hardware tools, speed and simplify the process of optimising and debugging C applications intended for hardware implementation".
The Pro tools can be used to quickly explore many different optimisation strategies, including the effect of loop unrolling, pipelining and stage delay strategies, with the goal of increasing overall system speed.
Further reading
Programming tools support floating-point libraries
Impulse Accelerated Technologies has announced support for Xilinx floating point libraries in its Impulse C software-to-hardware compiler.
Development system accelerates supercomputing
Global supercomputer leader Cray is working with Impulse Accelerated Technologies to help programmers speed up applications running on the Cray XD1 supercomputer.
During this process, the developer may actually discover that a particular loop or C software process can achieve higher overall throughput at a lower clock speed - and therefore lower power consumption - with only a nominal increase in generated hardware resources by virtue of automated pipelining and instruction scheduling.
"This level of analysis through experimentation would be virtually impossible using traditional HDL coding methods", stated Pellerin.
After hardware is generated, in the form of automatically generated VHDL or Verilog output files, the application developer can further analyse the application by using the interactive, cycle-accurate CoDeveloper Pro debugger.
This tool translates the generated HDL into a cycle-accurate C-language representation that can be compiled and run in a software simulation environment.
The resulting C-language simulation model can then be stepped through, on a cycle-by-cycle basis, to test to determine which C language statements (in the original application source code) are active in any given clock cycle.
This can be particularly useful for analysing the efficiency of the generated hardware, as well a being useful for analysing bit- and cycle-accurate behaviour, prior to running more comprehensive HDL simulations.
The CoDeveloper Pro Interactive Optimiser has cycle-annotated, expanded C source code display, C code block summaries, including loop latencies and pipeline rates, a dataflow graph showing parallel hardware generation, interactive editing of pipeline stage delay constraints and an automated pipeline graph showing loop latency and rate tradeoffs.
The CoDeveloper Pro Cycle-Accurate Debugger has interactive, C source-level debugging with cycle-accurate behaviour, variable watch window, colour coded, cycle-annotated source code display, single-cycle and multiple-cycle stepping controls and stream I/O displays.
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