Design tools allow high-performance C compiling

The newest edition of Impulse's CoDeveloper C to RTL design tools allows FPGA users to compile C to Altera's highest-performance programmable platforms.

HDLs do a good job of capturing logic functionality in a generic and synthesisable way.

In a similar fashion, high-level languages do a good job of capturing software personality in a standard yet flexible way.

In modern designs which target FPGAs or ASICs, both embedded processors (which need to run code) as well as custom logic (generated by a sort of code) have to live side by side and even overlap in some cases, especially if a processor core is soft and synthesisable.

Here, the tools which tie the design together must me tightly coupled and somewhat homogenous.

We are all familiar with having to learn different tools, with different commands, and different interfaces to meld in a specific project.

Sometimes it works out well, other times it's pushing a donkey from behind.

C to synthesis is not a new concept, but it is moving to the next level thanks to Impulse.

The newest edition of its CoDeveloper C to RTL design tools allows FPGA users to compile C to Altera's highest-performance programmable platforms.

By adding support for Altera's SOPC Builder and the Quartus II, Version 4.1 design software, the CoDeveloper makes it possible to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB.

Once compiled, applications map directly to Cyclone or Stratix devices without writing low-level VHDL or Verilog.

In addition, CoDeveloper can generates the Avalon interface used in SOPC Builder.

This can reduce prototype and end-product development time.

It allows for a new iterative process to occur in the system design.

Initially, functionality can be tested and verified using compiled C running inside a hard core.

But, when bottlenecks are identified which need to be accelerated, sections of the code can instead be compiled to logic.

This permits types of functional partitioning that couldn't be done before.

According to Impulse, "The compiler analyses untimed C code and collapses multiple C statements and operations into single-clock instruction stages".

"CoDeveloper unrolls loops and generates loop pipelines to exploit the extreme levels of parallelism possible in an FPGA".

"Hardware acceleration of up to 300x over code running on embedded processors has been demonstrated".

"This is a pretty exciting possibility to any embedded system on a chip designer facing real time bottleneck issues due to limitations of a core processor".

With a little time and effort, designers can create their own libraries of specialise IP targeting their specific applications in a very optimised way.

CoDeveloper automates the creation of hardware/software interfaces and generates synthesisable HDL outputs compatible with popular FPGA synthesis tools.

Additional CoDeveloper outputs can be exported to generated IP blocks for the Altera SOPC Builder environment.

This makes it possible to create high-performance, mixed hardware/software applications for Altera programmable platforms without the need to write low-level VHDL or Verilog.

The tools which tie this together are highly parallel and graphically oriented.

CoDeveloper allows FPGA algorithms to be developed in C/C++ development environments.

Then, by using the Application Monitor program, users can generate debugging visualisations for highly parallel, multi-process applications.

This helps identify dataflow bottlenecks and other areas for acceleration.

SOPC Builder combined with CoDeveloper also supports designs using processors external to the FPGA.

The memory mapped interfaces are automatically created by CoDeveloper for hardware/software communication.

The software has been tested with current designs for image processing, data encryption, communications, neural simulation and genomics.

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