Product category:
Design and Development Software
News Release from: Impulse Accelerated Technologies | Subject: C to RTL design tools
Edited by the Electronicstalk Editorial
Team on 20 September 2004
C to RTL tools support design software
CoDeveloper makes it possible to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB
Impulse Accelerated Technologies has announced the newest edition of its CoDeveloper C to RTL design tools, which adds support for Altera's SOPC Builder and the Quartus II, Version 4.1 design software CoDeveloper makes it possible to describe, debug and test mixed hardware/software applications using standard C development tools such as Visual Studio and GCC/GDB -- and compile those applications directly to Cyclone or Stratix devices without writing low-level VHDL or Verilog
This article was originally published on Electronicstalk on 29 Sep 2004 at 8.00am (UK)
Related stories
Design tools allow high-performance C compiling
The newest edition of Impulse's CoDeveloper C to RTL design tools allows FPGA users to compile C to Altera's highest-performance programmable platforms.
Software adds C-based FPGA design input
CoDeveloper C-to-FPGA tools from Impulse Accelerated Technologies can now be integrated with advanced FPGA synthesis and verification tools from Synplicity.
CoDeveloper optionally generates the Avalon interface used in SOPC Builder, greatly reducing prototype and end-product development time.
The Impulse C function libraries included with CoDeveloper allow FPGA algorithms to be developed in C/C++ development environments.
CoDeveloper's Application Monitor generates debugging visualisations for highly parallel, multi-process applications, helping system designers identify dataflow bottlenecks and other areas for acceleration.
Further reading
Programming tools support floating-point libraries
Impulse Accelerated Technologies has announced support for Xilinx floating point libraries in its Impulse C software-to-hardware compiler.
Development system accelerates supercomputing
Global supercomputer leader Cray is working with Impulse Accelerated Technologies to help programmers speed up applications running on the Cray XD1 supercomputer.
Software optimises C-based FPGA designs
Impulse Accelerated Technologies has released its CoDeveloper Pro optimisation and debugging software to complement its CoDeveloper C-to-FPGA compiler.
CoDeveloper's advanced parallelising compiler generates synthesisable HDL outputs from ANSI C inputs.
The compiler analyses untimed C code and collapses multiple C statements and operations into single clock instruction stages.
CoDeveloper unrolls loops and generates loop pipelines to exploit the extreme levels of parallelism possible in an FPGA.
Hardware acceleration of up to 300x over code running on embedded processors has been demonstrated.
CoDeveloper's Impulse C libraries also allow software programmers to take advantage of system-level parallelism by providing a multi-process, streaming programming model appropriate for a wide variety of computationally intensive applications.
CoDeveloper automates the creation of hardware/software interfaces and generates synthesisable HDL outputs compatible with popular FPGA synthesis tools including Altera's Quartus II software tools.
Additional CoDeveloper outputs simplify exporting generated IP blocks to the Altera SOPC Builder environment.
This makes it possible to create high-performance, mixed hardware/software applications for Altera programmable platforms without the need to write low-level VHDL or Verilog.
The CoDeveloper tools provide a natural bridge between C language programming and FPGA hardware design.
According to Joe Hanson, Director of Marketing for System Level Tools at Altera, "CoDeveloper is an excellent complement to existing software and FPGA development tools".
"The Impulse C philosophy is to allow parallelism to be expressed at the system level - within the context of standard ANSI C - while the CoDeveloper compiler frees programmers from the drudgery of extracting process-level parallelism and creating equivalent HDL code".
"With SOPC Builder support, the connectivity of these specialised blocks to other system resources is fully automated".
The addition of SOPC Builder support extends CoDeveloper to allow mixed hardware/software application design using embedded processors such as Altera's Nios II as well as processors external to the FPGA.
The required memory mapped interfaces are automatically created by CoDeveloper for hardware/software communication, and all hardware/software files required for integration with Altera SOPC Builder are also generated.
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