Physical synthesis for multi-million-gate designs

Incentia Design Systems has entered the physical synthesis market with a new software product DesignCraft Pro.

Incentia Design Systems has entered the physical synthesis market with a new software product DesignCraft Pro.

DesignCraft Pro delivers solutions from RTL to detailed placement with DFT and low power options.

It is a natural extension of Incentia's static timing analyser, TimeCraft, and logic synthesiser, DesignCraft, both announced last year.

All three products use a unified, tape-out proven timing engine to ensure timing consistency between implementation and timing sign-off.

Based on its patented technologies, DesignCraft Pro effectively addresses the issues of timing closure, design capacity, and turnaround time, for multi-million-gate nanometer designs.

"Our goal has always been to provide a complete timing and synthesis solution for nanometer designs", said Dr Shing-Chong Chang, VP of Product Management of Incentia.

"Since the announcements of TimeCraft and DesignCraft products last year, we have had tremendous acceptance of our integrated timing and synthesis tools.

Now with DesignCraft Pro, we are strengthening our product offerings for design timing closure between synthesis and layout".

Dr Chang noted, "We have already shipped DesignCraft Pro to several customers in the multi-media, networking and communication design areas".

"We believe DesignCraft Pro is very helpful in solving timing closure problems between synthesis and layout.

On one of our recent designs, we were struggling with timing closure between synthesis and layout, even though synthesised netlist met the timing.

We tried DesignCraft Pro and it proved its competence by shaving two nanoseconds off the most critical path, and we taped out the design successfully", said Becker Sze, Senior Design Manager of AverLogic Technologies, San Jose, Calif.

Thanks to its patented technology and flexible hierarchical software architecture, DesignCraft Pro runs faster while consuming less memory.

It handles designs of up to 5 million gates on 32bit platform workstations, and runs two- to five-times faster than alternative solutions while producing superior timing results with setup time, hold time, design rule fix and area recovery, all simultaneously optimised.

A 64bit version is available for larger designs.

During today's IC implementation flow, one of the most frustrating problems facing designers is the inconsistency of timers between implementation and timing sign-off.

Incentia eliminates this frustration by using a unified timing engine from TimeCraft, a customer-proven static timing analyser with many tapeouts.

This provides consistent constraint handling and timing analysis at every step of the design flow: synthesis, placement, optimisation and timing signoff.

In addition, DesignCraft Pro offers rich features for power/ground (PG) routing, I/O port optimisation and planning, macro placement and floorplanning, various placement obstruction handling and a GUI for layout editing and crossreferencing among source code, schematic, hierarchy and layout views.

DesignCraft Pro supports industry standard formats such as.lib, LEF and GDSII for libraries; SDC for timing constraints; Verilog and VHDL for designs; and DEF and PDEF for layout data.

DesignCraft Pro is shipping now.

Pricing begins at $100,000 (USD) for a one-year time-based license.

It runs on Sun Solaris 32bit and 64bit OS, HPUX-11, and Linux platforms.

It is compatible with tool flows from other EDA companies such as Synopsys, Cadence and Avant!.

(This was Electronicstalk's Top Story on 20 May 2002).

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