Timing analyser speeds to faster signoff

Incentia Design Systems has improved the performance of its TimeCraft full-chip gate-level static timing analyser for multi-million-gate high-performance designs.

Incentia Design Systems has improved the performance of its TimeCraft full-chip gate-level static timing analyser for multi-million-gate high-performance designs.

Continuing its lead in analysis speed and capacity for large designs, Incentia's new TimeCraft release improves its runtime up to 5x and reduces memory utilisation up to 30% on large designs, when compared with the previous release.

TimeCraft's performance gains are the result of the refinement of its proprietary "incremental timing exception reduction" (ITER) technologies and new techniques for timing path tracing and management.

These improvements have greatly reduced customers' turnaround time for ECO timing iterations and final signoff, and increase productivity.

"This new TimeCraft release supports our position as a technology leader in the STA market", remarked Ihao Chen, President and CEO of Incentia.

"Our customers are pleased with our speed advantage over competing tools.

Now, a 10-million-gate design can be analysed in less than 30min on a 32bit platform".

"TimeCraft has a speed advantage over competing tools.

With it, our timing verification turnaround time has been reduced by up to tenfold.

We are successfully applying TimeCraft to image processing ICs used in our copier and printer products.

We are pleased with TimeCraft's speed enhancements, its quality and the resultant productivity improvements for our large SoC designs", remarked Zenji Oka, Manager of CAD Engineering Section, Imaging System LSI Development Centre, Ricoh Co.

"We have adopted TimeCraft for our design flow because of its speed and capacity advantages over competing tools.

It drastically reduces the total verification time on our designs with complex timing constraints.

With TimeCraft, we expect to realise a productivity impact on our future SoC designs", noted Yoshio Okamura, Executive Manager of Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp.

"We have used TimeCraft for the timing iteration and signoff stages of our designs, such as the recent tapeout of a RAID controller chipset fabricated using TSMC 0.18um process.

We completed the project ahead of schedule due to TimeCraft's quick turnaround time.

We plan to continue to use TimeCraft for our future designs", added Vincent Lin, Assistant Vice President of R and D, Promise Technology.

TimeCraft is a fast, gate-level, full-chip static timing analyser for timing signoff and ECO timing iterations for multi-million gate, high-performance designs.

It supports both SDF and DSPF flows and takes the full set of Synopsys Design Constraints (SDC).

TimeCraft offers rich features required in analysing different kinds of designs.

It has been used to successfully tape out numerous customer designs in chipset, networking, communication, multimedia and wireless applications.

TimeCraft pricing starts at $20,000 (US list) per year for a three-year subscription and is available now for Sun Solaris (32 and 64bit), HP (32 and 64bit) and Linux platforms.

Back to top