Product category:
Design and Development Software
News Release from: Incentia Design Systems
Edited by the Electronicstalk Editorial
Team on 17 July 2003
Toshiba picks static timing analyser
Toshiba has selected Incentia's TimeCraft full-chip gate-level static timing analyser for timing verification of its multi-million-gate high-performance SoC designs.
Toshiba has selected Incentia's TimeCraft full-chip, gate-level static timing analyser (STA) for timing verification of its multi-million-gate, high-performance SoC designs Toshiba and Incentia have signed a multi-year agreement for widespread use of TimeCraft
This article was originally published on Electronicstalk on 21 May 2002 at 8.00am (UK)
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"As our design sizes continue to increase and timing constraints get more complex, reducing total timing verification turnaround time has become very critical for meeting our design schedule", remarked Tamotsu Hiwatashi, Senior Manager, Planning Department, System LSI Design Division, Toshiba Corporation.
"TimeCraft satisfies our stringent STA requirements with it features, speed and capacity.
Its fast analysis drastically shortens our total STA turnaround time.
We are pleased with TimeCraft's performance and expect to see even more productivity improvements with future larger designs".
"It is a great recognition that Toshiba, one of the world leaders in electronics and semiconductors, has selected TimeCraft.
We look forward to working closely with Toshiba's SoC design teams", added Ihao Chen, President and CEO of Incentia.
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