Product category:
Design and Development Software
News Release from: Incentia Design Systems | Subject: TimeCraft
Edited by the Electronicstalk Editorial
Team on 19 July 2006
Timing analyser handles 20-million-gate
designs
NEC Electronics' EMMA project team has successfully taped out designs with up to 20 million gates using Incentia's TimeCraft static timing analyser and its advanced on-chip-variation analysis.
NEC Electronics' EMMA project team has successfully taped out designs with sizes of up to 20 million gates, using Incentia's TimeCraft static timing analyser (STA) and its advanced on-chip-variation (OCV) analysis feature The built-in advanced OCV capability improves accuracy and efficiency for nanometre design timing analysis
This article was originally published on Electronicstalk on 9 Jun 2003 at 8.00am (UK)
Related stories
Timing analyser speeds to faster signoff
Incentia Design Systems has improved the performance of its TimeCraft full-chip gate-level static timing analyser for multi-million-gate high-performance designs.
Upgrade speeds synthesis and timing software
The latest versions of TimeCraft, DesignCraft and DesignCraft Pro feature improved runtime, capacity and quality, when compared with the 2003.09 release.
"We used TimeCraft and its advanced OCV analysis feature for modelling on-chip statistic process variations for designs", said Masao Hirasawa, General Manager, Digital Audio/Visual Systems Division, NEC Electronics.
"TimeCraft and its advanced OCV feature met our stringent requirements and demonstrated excellent results".
"We have successfully taped out designs with gate count sizes of up to 20-million gates and dramatically shortened our design cycle".
Further reading
Software upgrades static timing analysis
TimeCraft software has an advanced on-chip-variation capability for improving the accuracy and efficiency of static timing analysis for 90 and 65nm designs.
Physical synthesis for multi-million-gate designs
Incentia Design Systems has entered the physical synthesis market with a new software product DesignCraft Pro.
"TimeCraft is a preferred timing sign-off tool for nanometre designs".
"We are pleased that TimeCraft was adopted as a nanometre sign-off STA by the EMMA project team, one of the leading design groups at NEC Electronics, a world-renowned semiconductor company", remarked Ihao Chen, President and CEO of Incentia.
"NEC Electronics' tape-out success and productivity gain with TimeCraft and its advanced OCV demonstrates our promise to support customers with the most advanced timing analysis technology for nanometre designs".
TimeCraft is a full-chip, gate-level STA for timing signoff.
It is the fastest STA available.
Its features, including comprehensive timing checking and reports, a built-in delay calculator, multiple supply voltage analysis, multi-task capability for multicorner and multimode analysis, and advanced phase lock loop (PLL) handling, all enable analysis on a large variety of design styles.
TimeCraft has runtime and capacity advantages that dramatically reduce timing verification turnaround time.
TimeCraft's advanced OCV feature addresses the effects of statistical on-chip process variations.
Traditional OCV uses a constant derating factor and may impose unnecessary performance penalties on nanometre designs.
These penalties include reduced performance, larger die sizes and longer design cycles.
TimeCraft's advanced OCV uses variable derating factors based on the logic level and physical location to select the optimal derating factor for each timing path.
This results in fewer timing violations, and allows design teams to rapidly achieve timing closure.
The native engine-based implementation approach is easy to use and delivers unparalleled performance in runtime and memory usage.
• Incentia Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
