Virtual prototyping added to system design tools

Innoveda is to provide a more powerful version of its Visual Elite tool that enables engineers to design from the system-level down to the register transfer level (RTL).

Innoveda is to provide a more powerful version of its Visual Elite tool that enables engineers to design from the system-level down to the register transfer level (RTL).

Visual Elite V2, scheduled to be available later this month, provides virtual prototyping capability and support for full SystemC, C/C++, VHDL and Verilog; and supports Unix- and Windows-based platforms.

Innoveda also announced major enhancements for its Fusion/SpeedWave high-performance VHDL simulation tool, including the support of VHDL-AMS in September.

Visual Elite V2 features enhanced virtual prototyping.

This is a powerful way to create a virtual model of the system hardware along with the software interface, early in the software design flow process.

The hardware/software design flow is supported at the implementation level by the integration of Visual Elite with Innoveda's V-CPU and Regent tools in a single SLD flow.

This combination provides co-verification and software interface modeling from a requirement and functional level down to HDL and memory-mapped registers.

V-CPU establishes a high-performance, integrated, hardware/software coverification platform, while Regent provides a tool to design and manage the system registers that interface between the hardware and software.

With both V-CPU and Regent, Innoveda is the first to offer a complete codesign environment including the hardware/software interfaces, high-performance coverification platform and the ability to provide hardware/software prototypes in a single tool.

Guy Moshe, Innoveda's senior vice president, System-Level Design group, said, "Innoveda is building next-generation tools for system-level design that employ emerging methodologies along with proven, well established technologies in different domains.

Until now, different tools were required individually for system, hardware and software in the design flow.

Innoveda's SLD tool suite, augmented by new design methodologies, enables us to link more of the system into a unified design environment".

The new high-level system analysis capability in Visual Elite V2, based on the technology in Innoveda's eArchitect tool, will enable users to create high-level functional and architectural models early in the design cycle, and estimate the performance of the functional model for different hardware/software partitioning.

Users will be able to define high-level events and dataflow in the system, such as bus or network transactions, data processing events, cause and effect relationships, and error conditions.

A set of analysis tools will enable users to analyse these high-level events during and after simulation.

Users of Visual Elite will have a choice of mixed SystemC, C/C++, VHDL and Verilog modeling to design at various levels of abstraction throughout a single flow and methodology.

SystemC and C/C++ designs can be captured easily in block diagrams, configurable macros and text templates.

The unified, integrated flow for the various languages and design abstraction enables better integration and a shorter learning curve for companies starting to use C/C++ and SystemC.

Innoveda has significantly improved the Vital simulation performance of its Fusion/SpeedWave high-performance VHDL simulation tool by up to a factor of 100.

This results in a dramatically shorter verification cycle at the RTL and gate level.

This enhanced version of Fusion/SpeedWave is available now.

In addition, Innoveda is integrating Version 6.0 of VCS from Synopsys for Verilog designers, to deliver up to five times the simulation performance for gate-level designs and twice the performance for RTL designs.

This new release is scheduled to be available in July at no additional cost to customers under current maintenance.

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