Product category:
Analogue and Mixed Signal ICs
News Release from: Inphi Corp | Subject: EDC and CDR devices
Edited by the Electronicstalk Editorial
Team on 25 April 2008
Signal processor works with SFP+ modules
Inphi's patented and field proven analogue signal processing engine delivers a high-performance low-power EDC/CDR product for use in 10Gbit/s Ethernet modules.
Inphi Corp has successfully demonstrated the interoperability of its electronic dispersion compensation (EDC) and clock data recovery (CDR) technology at the SFP+/EDC interoperability plugfest, hosted by the Ethernet Alliance at the University of New Hampshire Interoperability Lab (UNH-IOL) Inphi's device, paired with every SFP+ optical module present at the event, met and exceeded the 10 Gigabit Ethernet (IEEE802.3ae) transmitter optical eye mask and jitter requirements
This article was originally published on Electronicstalk on 13 Oct 2004 at 8.00am (UK)
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In addition, the device demonstrated error-free performance as a receiver behind all SFP+ modules when put against the worst optical transmitter.
Inphi's patented and field proven analogue signal processing engine delivers a high performance, low power EDC/CDR product for use in 10Gbit/s Ethernet modules and systems.
In addition, as an established vendor of transimpedance amplifiers (TIAs), Inphi is well positioned to address the system challenges between SFP+ modules and its physical layer devices on a line card.
Further reading
Clock driver performs in DDR2 tester
CST has selected the Inphi INCU877 PLL clock driver IC as the memory clock buffer for use on the CST SP3000-DDR2 tester.
Buffers are ready for next-generation memories
Inphi Corp has released the world's first registered buffer with parity checking operating at 400, 533 and 667Mbit/s using second-generation double-datarate (DDR2) technology.
The testing was recently held at the University of New Hampshire Interoperability Lab (UNH-IOL) by the Ethernet Alliance SFP+/EDC subcommittee, and demonstrated multiple SFP+ SR and LR optical transceivers and physical layer (PHY) ICs interoperating over 270m of OM3 multimode fibre and 10km of single-mode fibre.
In addition, the group demonstrated multiple SFP+ -SR and -LR optical transceivers and PHY ICs interoperating with Xenpak, X2 and XFP optical transceivers over the same distances.
"The success of this plugfest indicates the readiness of silicon and module vendors to support SFP+ platforms, which will enable mass adoption of 10 Gigabit Ethernet", said Marco Mazzini of Cisco and the Technical Champion of the Ethernet Alliance SFP+/EDC Subcommittee.
SFP+ modules are hot-pluggable, small-footprint optical transceivers intended for datacom applications.
SFP+ interfaces offer the smallest, lowest-power solution for 10 Gigabit Ethernet to enable increased density in enterprise applications.
SFP+ modules and PHY ICs are being developed for SR, LR, LRM (long-wavelength multimode) and ER (extra-long wavelength) optical reaches per IEEE802.3ae-2002 and IEEE802.3aq-2006.
Electrical and mechanical interface specifications for SFP+ modules, direct attach cables and hosts are under definition by the SFF Committee, a multiple-source agreement group with broad industry participation.
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