Tools validate embedded memories

STMicroelectronics' Central R and D division is using InnoLogic's ESP-CV to eliminate functional bugs in its embedded memories.

STMicroelectronics' Central R and D division is using InnoLogic's ESP-CV to eliminate functional bugs in its embedded memories that are included in major product lines such as telecomms and datacommunications and consumer and automotive electronics.

Dian Yang, President and CEO of InnoLogic, noted, "A leading semiconductor company like STMicroelectronics needs the confidence that they are delivering high-quality products to the market.

ESP-CV enables designers to achieve complete functional verification coverage of embedded memories-something that they have not been able to accomplish using mainstream verification solutions".

"As designs move toward 90 nanometres and below, we see increasing verification challenges for full custom silicon elements, such as embedded memories that occupy a growing portion of SoC designs", added Yang.

"Adding ESP-CV to the design flow saves significant engineering time and gives customers the confidence that their product will work as designed and verified".

Philippe Magarshack, Group Vice President of Central R and D, Design Automation for STMicroelectronics explained, "The families of SRAMs and ROMs generated by our memory compilers as well as embedded DRAMs are found in just about every significant microelectronics product that we manufacture.

The presence of even one functional bug in these embedded memories could have a significant impact on our business.

Before we had ESP-CV, we had to verify the HDL models and Spice circuits separately using traditional simulation, which not only was incomplete, but also consumed significantly more internal resources".

Magarshack continued, "InnoLogic's ESP-CV has enabled us to implement an automated flow to directly verify the functional equivalence of dozens of HDL models and Spice netlists created by our memory compiler.

This significantly enhanced our overall design quality and productivity".

Instead of requiring manual translation of a Spice netlist to a Verilog gate-level netlist, which can be time-consuming and error prone, ESP-CV automatically reads the Spice netlist and its parasitic information for equivalency checking.

With ESP-CV, STMicroelectronics was able to find and fix functional bugs like incorrect data storage handling of their highly complex SRAM models with aggressive pre-charge techniques.

By streamlining the verification process of compiler generated embedded SRAMs, ROMs and DRAMs, STMicroelectronics expects to increase the quality of their embedded memories and get their silicon to market faster.

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