Product category:
Design and Development Software
News Release from: InnoLogic Systems
Edited by the Electronicstalk Editorial
Team on 13 March 2003
Harmony of tools to speed SoC
verification
InnoLogic has joined the Novas Software Harmony partner programme.
InnoLogic has joined the Novas Software Harmony partner programme The two companies have had a long-standing relationship in that users of InnoLogic's ESP-CV, a product that verifies the functional equivalence between behavioural or RTL models and the Spice-level netlist of full custom designs, can use Novas' Debussy debug system to investigate the causes when these models do not match
This article was originally published on Electronicstalk on 11 Mar 2003 at 8.00am (UK)
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Virage Logic is using ESP-CV as part of its quality assurance programme to further increase the quality of its ASAP Memory product line.
InnoLogic's joining Novas' Harmony programme further strengthens the existing relationship between the two companies and improves the quality of the interoperability and support that the two companies provide for their mutual customers.
Dian Yang, President and CEO for InnoLogic noted, "InnoLogic is focused on solving the verification challenges presented by the increasing amount of full custom silicon content in SoC designs as well as providing verification solutions that help our customers increase the overall quality of their designs.
As a result, we are always looking for partner opportunities that will enhance our product offerings.
Further reading
Functional verification checks out memory IP
InnoLogic's ESP-CV product is now an integrated part of the overall verification process at Artisan Components.
Toshiba opts for simulation analysis solution
Toshiba Corp has adopted the FineSim hybrid simulation analysis solution into its design flow.
InnoLogic's ESP-CV enables designers to achieve complete functional verification coverage of embedded memories and other full custom components within SoC designs.
And, Novas' Debussy debug system aids designers in resolving overall design errors.
The combination of our two companies' product solutions gives our customers a significant edge in the overall quality and confidence of their SoC products".
Scott Sandler, President and CEO of Novas stated, "The increasing complexity and growing custom silicon content of today's SoC designs makes them very difficult to understand and leads to very challenging verification issues.
Novas focuses on cutting debug time by making it easier for engineers to find the causes of design behaviour.
Novas is committed to partnering with companies that are on the leading edge of addressing these issues.
InnoLogic's ESP-CV offering is one of the leading solutions for verifying the custom silicon content in SoC designs.
We believe enhanced interoperability between ESP-CV and Debussy delivers a more productive verification experience for our shared customer base".
Engineers designing full custom circuits such as SRAM, DRAM, Flash, and cache use ESP-CV to verify the functional equivalence of the implementation Spice netlist and the behavioural model used for simulation.
When a mismatch is found between these two independently generated models, a counter example is generated for debugging.
With the interoperability between Novas' Debussy debug system and InnoLogic's ESP-CV, designers can quickly isolate errors and identify the source of the problem.
The integration of these products further increases the productivity of full custom design verification.
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