RTL planner and floorplanner debut at DAC

InTime Software will unveil two new products, Time Planner for RTL planning and Time Builder, a hierarchical gate-level floorplanner, at the Design Automation Conference next month in New Orleans.

InTime Software will unveil two new products, Time Planner for RTL planning and Time Builder, a hierarchical gate-level floorplanner, at the Design Automation Conference (DAC) next month in New Orleans.

The products are part of InTime's Physical First design flow.

Together with InTime's Time Architect, a pre-RTL chip estimator, these two new products raise IC design to a higher level of abstraction and allow early timing closure orders of magnitude faster on huge SoC, ASIC and ASSP designs.

Altogether the three products expand and enhance the concept of the Silicon Virtual Prototype (SVP), a name that is being applied to a new generation of EDA tools that raise design planning to RTL.

"Going directly from RTL to a physical floorplan allows Time Planner to operate faster and at an even higher level of abstraction than other systems, while using accurate parasitic data generated from a physical layout", commented George Janac, founder and president of InTime.

"This approach allows us to model large nets up front, instead of trying to retrofit or perform large net handling once gate-level mapping has been established".

Designers of deep submicron (DSM) circuits are familiar with design convergence problems uncovered during the later stages of design.

SVP systems attempt to remedy area and timing-related problems by enabling designers to catch and correct them during the RTL stage.

But the typical SVP approach requires a completed netlist, and uses a form of synthesis to map RTL to gates.

This locks in timing before a physical plan is developed and without knowledge of actual placement or parasitics.

InTime's Physical First methodology goes directly from RTL to a physical floorplan, and from that derives parasitics based on placement.

Designing with the right parasitics at this early stage is a key distinction that enables InTime to deliver greater scalability, capacity and flexibility for design optimisation by third-party synthesis and physical design systems, including those from Cadence, Synopsys and Avant!.

Time Architect expands the SVP model by creating a handoff point before RTL.

Before any RTL is written, the Time Architect predicts chip area, power, and yield and generates a plan and datasheets, encapsulating design intent and enabling designers to quickly compare the impact of different intellectual property (IP) components on complex ICs.

This plan is used by the RTL design team as they develop RTL and is passed into InTime's new Physical First RTL planning system.

Time Planner reads in RTL and generates a physical floorplan directly from RTL without mapping to gates.

Time Planner manages and handles a mix of design IP, RTL, and even unfinished RTL.

Time Planner has an embedded static timing analysis tool that has been specifically designed to assess timing issues fast at the RTL stage.

Once RTL Timing has been performed, the design team can easily explore and debug critical nets, as nets on the floorplan and in the RTL code are correlated visually.

Time Planner then generates synthesis constraints that drive third-party synthesis tools, enabling them to quickly process huge multi-million-gate designs.

It also generates logical, synthesis and physical hierarchies.

Time Planner benefits from InTime's powerful morphing placement system that shapes blocks during placement to optimise area usage.

Capabilities include global block placement, internal budgeting analysis, full power routing, block assembly, and I/O placement.

Time Planner also performs automatic partitioning for optimal physical bounding.

Interactive capabilities include control over placement of top-level pins and definition of stripes and rings on macros to accommodate routing.

The floorplan generated by Time Planner can be used as a starting point by Time Builder.

Time Builder is a hierarchical gate-level chip assembly floorplanner that can place any combination of gates, blocks, cells and RTL.

Time Builder has all the capabilities of Time Planner but adds hierarchy and even more powerful interactive capabilities that enable physical designers to easily traverse the design hierarchy and perform edits inside even hard blocks.

When blocks are moved, power and ground move with them and are updated on the fly.

Because Time Builder has unlimited capacity, it handles the largest deep submicron circuits.

With timing budgeting and static timing analysis embedded in both Time Planner and Time Builder, designs can migrate in parallel from RTL to gates while maintaining chip-level context and timing abstractions.

All InTime products integrate into design environments that use industry standard synthesis and place and route systems, and accelerate the flow through those systems to tape-out.

Time Architect, Time Planner, and Time Builder are available now.

Time Architect is priced starting at US $38,000.

Time Planner is priced starting at US $98,000 and Time Builder is priced starting at US $175,000.

All prices are for annual time-based licenses.

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