Bus buffers enable hot swapping

The hot insertion logic with precharge minimises disruptions on the ports and prevents data corruption on the bus during I/O card insertion into live backplanes.

New from Hendon Semiconductors, the IES5502 is a high-speed dual bidirectional bus buffer with hot insertion logic.

The IES5502 extends the functionality of the company's existing IES5501 to include hot insertion logic with precharge.

Both the IES5501 and IES5502 are compatible for extending and expanding I2C, SMBus, PMBus, IPMB and other similar two-wire bus systems.

The hot insertion logic with precharge on the IES5502 minimises disruptions on the ports and prevents data corruption on the bus during I/O card insertion into live backplanes.

The IES5502 also features very low input-output offset voltages (typically only 75mV), allowing their use in a cascade or daisychain fashion.

Bus level translation (from 1.8 to 15V) is also incorporated into the IES5502 providing flexibility in interfacing systems of different technologies; speeds and loads simplifying the engineers design process.

The unique function of the IES5502 with hot insertion logic buffer provides one of the fastest response times of such bidirectional buffers without the use of rise time accelerators (RTAs).

The RTA when combined with low noise margins may cause glitches outside of the I2C specification.

The enable pin on the IES5502 is used to isolate sections of the bus and can be used to activate sections of the bus during system startup.

The features of the IES5502 makes it well suited for the computing or networking systems such as backplane applications within telecommunications systems (including AdvancedTCA) where there are differences in voltage levels and speeds.

It is also suited for use in field replacement units (FRUs) used in either a conventional fully bused arrangement or in radial architecture.

The IES5502 is offered in 8-pin SO and MSOP packages, all are RoHS compliant with samples available and is in full production.

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