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News Release from: Innovative Silicon | Subject: Z-RAM
Edited by the Electronicstalk Editorial
Team on 05 September 2005
Embedded memory exploits SoI floating
body effect
Z-RAM embedded memory technology for SoCs can double memory density when compared with existing embedded DRAM solutions.
Innovative Silicon (ISi) has launched its Z-RAM embedded memory technology for SoCs which can double memory density when compared with existing embedded DRAM solutions The Z-RAM (zero capacitor RAM) technology harnesses the floating body (FB) effect that occurs in silicon-on-insulator (SoI) devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor
This article was originally published on Electronicstalk on 24 Jan 2006 at 8.00am (UK)
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Innovative Silicon has announced availability its second generation Z-RAM technology, named Z-RAM Gen2, which delivers significant performance improvements with greatly reduced power consumption.
Z-RAM memory designs have been taped out at 90nm and the technology is scalable to 22nm design rules.
More, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials.
In SoI devices, the floating body or body charging effect which results in a charge developing in the FET device body has generally been considered as a parasitic effect.
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ISi has developed a mechanism to control and enhance this FB charge, which can then be used to store "1" or "0" binary states.
Information is read by comparing the current in a selected cell to a reference, using a current sense amplifier.
SoI is emerging as the process technology of choice for high performance SoCs and Microprocessors, with leading processor and games companies already switching away from bulk CMOS to take advantage of the increased performance and reduction in power that SoI delivers.
Explains ISi CEO, Mark-Eric Jones: "Embedded memory occupies at least 70% of the die area of today's complex SoCs".
"The combination of our Z-RAM memory - which requires less than half the die area required for traditional embedded DRAM, without the additional process steps required to embed traditional DRAM - and existing SoI processing, which additionally offers large performance and power benefits, means that not only are Z-RAM SoCs higher performance and lower power, they are also much cheaper than SoCs based on bulk CMOS wafers".
He continues: "By reversing the traditional economics and making SoI wafers a lower cost solution than bulk silicon for most SoCs and microprocessors, we expect our Z-RAM memory technology to accelerate the anticipated industry switch from bulk silicon to SoI.
As a result designers of cost-sensitive products will also be able to take advantage of the increased performance and lower power consumption of SoI".
Finally, Z-RAM technology does not require designers to compromise on speed or power: read and write operations in under 3ns have already been demonstrated on silicon; and ISi's low power Z-RAM option promises significant power savings compared with traditional embedded DRAM.
Concludes Jones: "Since Z-RAM technology uses a single transistor and no capacitor in the bitcell it is much more scalable than alternative DRAM and SRAM technologies".
"We have already demonstrated a Z-RAM memory cell using FinFET technology and expect Z-RAM to easily meet the high density embedded memory requirements of chip designers for the next 15 years". Request a free brochure from Innovative Silicon ...
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