Paper claims long future for novel memories

A paper given at the IEEE SOI Conference shows the manufacturability of Z-RAM capacitor embedded memory technology in FinFET and TriGate devices with geometries below 45nm.

A new paper given by Innovative Silicon (ISi) at the IEEE's SOI Conference in Honolulu, claims to prove the manufacturability of its Z-RAM capacitor embedded memory technology in FinFET and TriGate devices with geometries below 45nm.

Z-RAM memory arrays have already been successfully demonstrated on silicon using partially depleted SOI structures, and the experimental results presented in ISi's new paper ensure that the technology will scale to 45nm and beyond.

In the recently introduced Z-RAM floating body memory cell, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET.

The charge stored in the floating body affects the device threshold voltage through the body effect and can be used to distinguish two states.

This eliminates the need for a capacitor element, so the resulting memory cell structure is based solely on a single transistor.

Therefore, Z-RAM memories can achieve five times the density of embedded SRAM and twice the density of embedded DRAM designs.

For the first time, new experimental work by ISi - presented in the IEEE paper co-authored by ISi's CTO Pierre Fazan and personnel from TI, Infineon, Soitec and ATDF (a subsidiary of Sematech) - shows that good retention characteristics for a Z-RAM memory cell based on CMOS FinFET and TriGate devices can be measured.

This means that FinFET-based Z-RAM memories are manufacturable, enabling the production of very low cost DRAMs and eDRAMs for 45nm and sub-45nm generations.

Comments Pierre Fazan: "This summer the first silicon we received back from the foundry has successfully demonstrated our claims for the Z-RAM technology on SOI".

"This new work shows that the structure is highly scaleable and suitable for use in devices for the years ahead".

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