Embedded memory works on 90nm SoI process

Innovative Silicon has achieved silicon validation of Z-RAM memory arrays on 90nm SoI process technologies.

Innovative Silicon has achieved silicon validation of Z-RAM memory arrays on 90nm SoI process technologies.

The company has also validated its memory bitcell (which requires only one transistor and zero capacitors) in an additional 10 fabrication processes that include 130nm SoI, 90nm SoI and FinFET technologies.

The company expects to demonstrate working silicon in multiple 65nm processes later this quarter.

"This is a real inflection point for ISi", stated Mark-Eric Jones, President and CEO of ISi.

"The technical validation we have achieved, coupled with our recent announcement with AMD, demonstrates the value of our technology to leading semiconductor manufacturers".

ISi's Z-RAM technology was created to solve one of the biggest challenges for SOC designers, how to shrink die sizes when memory dominates chip area and cost.

With Z-RAM IP, IC manufacturers gain the benefit of having more dense memory which in turn means their SOCs, developed on SoI, can be produced at lower cost than those on bulk CMOS silicon.

ISi validated the Z-RAM technology at two separate locations - Freescale Semiconductor's Austin Technology and Manufacturing centre, and at a leading pure-play semiconductor foundry.

"We achieved outstanding results in these 90nm technologies", noted Dr Pierre Fazan, cofounder and CTO of ISi.

"I am particularly excited about our soft error rate (SER) data obtained on multi-megabit memory macros".

"This data shows our memory IP is an order of magnitude better than embedded SRAM technologies and comparable to the leading embedded DRAM technologies".

"This, coupled with our density and performance advantages, makes Z-RAM the ideal solution for anyone using large blocks of embedded memory".

ISi's Z-RAM (zero-capacitor DRAM) technology uses a single transistor to create an extremely dense, high-performance memory instance.

Embedded SRAM is the most widely used embedded memory technology and is based on a six transistor cell.

Embedded DRAM is a less-widely-used technology that uses a single transistor, single capacitor structure, providing much greater density than SRAM, but with lower performance, and, typically requiring changes to the semiconductor process.

Z-RAM harnesses the floating body (FB) effect of silicon on insulator (SoI) devices that enables state storage without a capacitor storage device.

Because the memory cell uses only a single transistor, Z-RAM is typically twice the density of embedded DRAM and five times the density of embedded SRAM, yet requires no exotic materials, no extra mask steps, and no new physics.

As embedded memories can comprise 70% of the area of a complex IC such as a microprocessor, memory density can be the single most important factor to overall system cost.

All semiconductor memories are subject to bit errors caused by radiation.

At terrestrial altitudes, the predominant sources of radiation include both cosmic rays and alpha particle radiation from radio-isotopic impurities in the package and chip materials.

When a bit error occurs, the affected memory cell will change to the opposite state - a 1 will become a 0, and vice versa.

This is known as a "soft error" as the semiconductor device is not damaged and the error is removed once the correct value is restored to the memory cell.

The rate at which these errors occur is known as the soft error rate (SER), and at a high enough level, these errors can significantly impact system reliability.

Recent analysis of ISi's Z-RAM technology performed by accelerated testing demonstrates that it is an order of magnitude less susceptible to the effects of ionising radiation than embedded SRAM - the dominant embedded memory technology - and is comparable to leading embedded DRAM technologies.

Back to top