SoC designers invited to meet at DAC

Innovative Silicon is organising meetings during DAC with SoC and microprocessor designers interested in reducing costs and improving the performance of their embedded memory implementations.

Innovative Silicon (ISi) is organising meetings during DAC with SoC and microprocessor designers interested in reducing costs and improving the performance of their embedded memory implementations.

Innovative Silicon (ISi) helps IC manufacturers reduce the cost of their complex ICs by 10 to 40% or more.

Its Z-RAM technology is one-fifth the size of embedded SRAM, the most widely used standard on-chip memory technology today, and requires no exotic materials, no extra mask steps and no new physics.

In fact, the company claims that there is no other step manufacturers can take that will deliver such dramatic cost savings with so little risk.

In comparison, current embedded DRAM technologies require a capacitor that is extremely difficult to shrink, requiring exotic designs and very expensive process modifications, which makes it very complex to scale to finer geometry process nodes.

"Our Z-RAM technology was validated in January of this year when we announced silicon results and that AMD had secured a full technology licence to use our ultra-dense memory IP in its future microprocessor products", said Jeff Lewis, Vice President of Marketing at ISi.

"And we'd like to extend an invitation for designers to engage with us at DAC to discuss their latest designs and how we can help them meet their performance and cost requirements".

Designers of memory-intensive applications using SOI or 90nm and finer geometries are encouraged to meet with ISi at DAC in San Francisco on Booth 1913 in the South Hall.

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