Innovation Award for capacitorless memory device

The 2006 Frost and Sullivan Product Innovation Award in the field of silicon-on-insulator (SOI) technology was presented to Innovative Silicon for the invention of the capacitorless memory device.

The 2006 Frost and Sullivan Product Innovation Award in the field of silicon-on-insulator (SOI) technology was presented to Innovative Silicon for the invention of the capacitorless memory device that overcomes the limitation in scaling dynamic random access memory (DRAM) for future memory needs.

Most volatile memory applications use DRAM because of its relatively simple structure and low-cost features.

However, as the scaling of semiconductor devices advances, DRAM is facing limitations in packing its capacitor ever smaller, squeezing the pitch of the device into dimensions previously deemed impossible.

DRAM design is encountering the physical limits of the materials while adopting strategies to maintain the performance of the shrinking device.

Innovative Silicon has developed the capacitorless one-transistor volatile memory device to eradicate the problems encountered in scaling the capacitor.

The capacitorless device, Z-RAM (which stands for 'zero capacitor RAM') offers performance similar to the standard six-transistor static RAM (SRAM) cell used in cache memory but only has a single transistor.

Without any capacitor, it is denser than conventional one-transistor, one-capacitor DRAM, which is used extensively in modern computers' main memory.

The large reduction in size allows a tremendous increment in memory densities and smaller total die area.

Z-RAM works by using floating body effect (FBE), a parasitic phenomenon first encountered in processor chip design, which is based on a new SOI process introduced in the early 2000s.

This effect causes capacitance to form between the transistor and the underlying insulating substrate, and was a problem that needed to be solved in conventional designs.

Researchers at Innovative Silicon have turned this parasitic effect into a useful feature by replacing the capacitor in a conventional DRAM cell with the capacitance between the gate and the buried oxide layer (BOX).

Thus, consisting of only one component instead of two, Z-RAM offers twice the density of DRAM, and six times that of SRAM.

Moreover, Z-RAM is compatible with the conventional SOI-complementary metal-oxide-semiconductor (CMOS) processes and does not need any additional masking steps or the introduction of any new materials.

SRAM is known to operate faster than DRAM and is preferred in high-speed applications such as level 1 cache where high speed is required.

Due to its small dimension, Z-RAM is normally much faster than DRAM and in a way, faster than SRAM.

The larger cell size of the SRAM occupies a larger real estate on the processor chip area.

This means that the capacitance induced by the long conduction paths, which carry current into the cells, could delay the driver circuitry.

Although Z-RAM's individual cells are not as fast as SRAM, the lack of the long conduction paths allow a similar amount of cache to be run at roughly the same speeds by avoiding this delay.

Innovative Silicon executives claimed that response times as low as 3ns have been achieved.

In addition, Innovative Silicon has shown that this technology is less susceptible to soft errors than SRAM and comparable with embedded-DRAM.

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