Product category:
Exhibitions, Courses, Conferences and Training
News Release from: Institution of Engineering and Technology
Edited by the Electronicstalk Editorial
Team on 26 August 2003
FPGA forum looks ahead to molecular
electronics
FPGA devices based on electronic nanotechnology and in particular molecular electronics hold the key to the future of computing and the sustainability of Moore's Law.
Field-programmable gate array (FPGA) devices based on electronic nanotechnology and in particular molecular electronics hold the key to the future of computing and the sustainability of Moore's Law This is the view of Prof Seth Goldstein, a keynote speaker at the IEE FPGA Developer's Forum on 21st and 22nd October 2003
This article was originally published on Electronicstalk on 30 Mar 2005 at 8.00am (UK)
Related stories
Semiconductor Executive Forum to be held in UK
The second IEE/FSA International Semiconductor Executive Forum brings together executives from the entire semiconductor industry, including fabless, foundry, test and packaging companies.
Engineers and technicians must be trained
Leading UK engineering and technology firms, with a combined multi-million pound spend on training and development, will assemble at the IEE 'Investing in Technical Teams' forum on 4 November 2004.
This new class of electronic device, termed chemically assembled electronic nanotechnology (CAEN), will be reconfigurable, low in power consumption, defect tolerant and provide very high component densities at significantly reduced manufacturing costs, according to Prof Goldstein, Carnegie Mellon University, USA.
"Within 10 years CAEN has the potential to offer orders of magnitude improvements in computing power and complete flexibility in terms of configuration and programming, without the huge upfront nonrecoverable engineering costs of developing an ASIC device", said Prof Goldstein.
"Whilst there is still much fundamental research to be completed, CAEN could represent the most significant advancement in the semiconductor industry since the development of CMOS manufacturing techniques in the 1960s", said Goldstein.
Further reading
Workshop gives complete picture on CE.NET 5.0
A UK-based workshop will give embedded software development engineers hands-on experience in running the new 5.0 release of Windows CE.NET on next generation processors.
DSP seminars focus on video applications
Abacus Polar is hosting two DSP seminars with Texas Instruments.
Latest Verilog standard released
IEEE 1364-2001, the Verilog hardware description language (HDL) standard, also known as Verilog-2001, was approved by the IEEE as a revised standard in March of this year.
Prof Goldstein will present a paper entitled "Reconfiguring the future" on the second day of the IEE FPGA Developer's Forum in London, UK.
Goldstein's work combined with the activities of a number of research institutions in Europe and US shows that CAEN offers the potential to enable electronic circuits to be constructed from single molecule switches interconnected by nanometre-sized wires.
CAEN-based devices are constructed from meshes of switches and wires, with a switch at the interconnection of each wire junction.
Once programmed a switch holds its state, which means additional devices are not required for programming and that the switch can be programmed and interrogated using the same set of wires.
The elegant simplicity of this approach removes much of the overhead required in traditional integrated circuits and means that up to 100 billion switches could be fabricated on a single square centimetre.
Individual switches within a device are very small: a single switch requires 100nm2 as opposed to 100,000nm2 for a traditional CMOS transistor.
This provides immediate power saving benefits as nano-scale devices require only a few electrons to cause a switch to change state.
Given the small geometries involved, CAEN is created using chemical self-assembly techniques instead of photolithography.
In one proposed architecture, called a nanofabric, a hierarchical process is used initially to create the molecular switches followed by two aligned groups of wires to form a two dimensional grid with the switches at the cross points.
A separate process is used to create a silicon-based die using standard lithography to provide power, clock lines, and I/O interface and support logic for the grids of switches.
Compared with traditional CMOS, CAEN devices have a higher defect density as a result of their scale and the chemical-based fabrication techniques.
Prof Goldstein is leading a team that is developing methods of handling defects through self-diagnosis and then implementing the desired computing functionality by programming around the defects.
Prof Goldstein will report on the latest advances in fabrication, modelling and programming of CAEN devices at the IEE Developer's Forum. Request free introductory details about products from Institution of Engineering and Technology ...
• Institution of Engineering and Technology: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
