Verification system checks IC boundary scan data

A new BSDL verification/creation system automatically extracts the boundary-scan structure from the silicon (chip) to create the BSDL file.

JTAG Technologies announces a new BSDL verification/creation system that automatically extracts the boundary-scan structure from the silicon (chip) to create the BSDL file, or if a BSDL file already exists, to verify its accuracy compared with the device.

The resulting BSDL file describes the boundary-scan characteristics of the device including scan register length, ID code (if present), instruction codes, and I/O lists.

JTAG Technologies announcement is a major step forward in assuring the quality of boundary-scan descriptive language (BSDL) files.

BSDL files are critically important in the preparation of boundary-scan based tests and in-system programming applications.

The BSDL verification system doesn't require in detail knowledge of the IEEE1149.1 and therefore it delivers great benefits to engineering and quality departments of IC developers, ASIC design groups, and test engineering departments by shortening time to market and error free BSDL files.

The BSDL verification system consists of BSDL verifier/creation software, the BSDL512 hardware unit supporting 512 I/O channels and the JT 3707 boundary-scan controller.

The system generates automatically a 100% accurate BSDL file, in compliance with IEEE1149.1, precisely corresponding with the boundary-scan logic implementation within an IC.

In addition to this capability it validates an already existing BSDL file thoroughly against an actual device.

The BSDL verification system is available now from JTAG Technologies.

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