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Lattice Semiconductor UK
Address:
1st Floor Rivermead House
Hamm Moor Lane
Addlestone
KT15 2SF
UK
Telephone: (UK) +44 1932 825700
http://www.latticesemi.com
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Listing of all 119 news releases from Lattice Semiconductor UK:
Design suite bundles industry's best FPGA tools
Latest FPGA design tools deliver up to 30% faster design compile times and support multiprocessor powered design compilation to achieve the fastest timing closure.
News from Lattice Semiconductor UK ( 7 May 2008)
Programmable logic saves portable power
With its low standby current, small form factor and instant-on operation, the ispMach 4000ZE family is ideal for handheld and portable equipment such as GPS systems.
News from Lattice Semiconductor UK (30 April 2008)
FPGA design tools add mixed language simulator
Active-HDL Lattice Edition will be bundled with the next version of Lattice's ispLever design tool suite.
News from Lattice Semiconductor UK (22 April 2008)
Embedded soft core processor adds uClinux option
Support allows developers to rapidly implement control systems in a design flow that builds on Lattice's open source embedded solutions approach.
News from Lattice Semiconductor UK (21 February 2008)
Low-cost serdes FPGAs available in volume
The LatticeECP2M devices are the industry's first low cost FPGAs to offer high-speed embedded serdes I/O, plus a pre-engineered physical coding sublayer block.
News from Lattice Semiconductor UK (18 December 2007)
IP library runs on 90nm embedded Flash FPGAs
Lattice Semiconductor has made available 45 ispLeverCore intellectual property and third-party vendor IP cores for its new 90nm embedded Flash LatticeXP2 FPGA family.
News from Lattice Semiconductor UK (28 June 2007)
FPGAs cut the cost of embedded serdes
Production volume prices have been reduced to as low as $9.95 for the 20K-look-up-table LatticeECP2M-20, cracking the $10.00 price barrier for the first time.
News from Lattice Semiconductor UK (27 June 2007)
Nonvolatile FPGAs promise more for less
Third generation nonvolatile FPGA family doubles maximum logic capacity, improves performance and adds dedicated DSP blocks.
News from Lattice Semiconductor UK (31 May 2007)
Programmable logic design suite is free to use
ispLever Classic is a comprehensive software design tool suite that supports all mature Lattice programmable devices.
News from Lattice Semiconductor UK (26 April 2007)
Design puts FPGAs into GPON receivers
Lattice Semiconductor has developed a Purespeed I/O burst mode receiver (BMR) FPGA reference design for gigabit passive optical networks (GPON).
News from Lattice Semiconductor UK (18 April 2007)
FPGAs have DDR interfaces to synchronous DRAM
FPGA's Double Data Rate 2 (DDR2) Synchronous DRAM memory interfaces operate at 533Mbit/s.
News from Lattice Semiconductor UK (15 March 2007)
Design tool suite expands FPGA support
Lattice Semiconductor has announced the immediate release of its latest ispLever design tool suite update, version 6.1 Service Pack 2.
News from Lattice Semiconductor UK (14 February 2007)
Extreme performance FPGAs enter volume production
The first members of the Lattice Semiconductor Extreme Performance LatticeSC and LatticeSC/M FPGA families have been fully qualified and released to volume production.
News from Lattice Semiconductor UK (26 January 2007)
Switch to ASIC cuts FPGA production costs
Lattice Semiconductor has announced the FreedomChip cost reduction methodology for its Extreme Performance LatticeSC and LatticeSCM FPGA families.
News from Lattice Semiconductor UK (23 January 2007)
Aldec software is tailored to Lattice FPGA lines
Lattice Semiconductor is to offer its customers a special edition of Aldec's Active-HDL Designer Edition tools for FPGA design.
News from Lattice Semiconductor UK ( 9 January 2007)
Cefriel joins Lattice Leader design program
Lattice Semiconductor has announced that Cefriel has joined the Lattice Leader Design Services Program, a highly select global network of companies.
News from Lattice Semiconductor UK (18 December 2006)
Lattice receives ISO/TS 16949 certification
Lattice Semiconductor has achieved certification of its quality systems to Automotive Industry Quality Standard ISO/TS 16949.
News from Lattice Semiconductor UK ( 7 December 2006)
65xx microprocessor core is made for FPGAs
An 8bit 65xx microprocessor IP core is now available from the Western Design Center, a new member of the ispLeverCore Connection IP partners programme.
News from Lattice Semiconductor UK ( 7 November 2006)
Programme member adds storage IP for FPGAs
IntelliProp, a comprehensive intellectual property (IP) and verification solutions provider focused on the storage industry, has joined the ispLeverCore Connections programme.
News from Lattice Semiconductor UK ( 3 November 2006)
Low-cost FPGAs gain PCI Express core support
PCI Express core is optimised for the newly announced LatticeECP2M low-cost FPGA family.
News from Lattice Semiconductor UK ( 2 November 2006)
Programmable clock buffers have more outputs
Tool suite expands FPGA design capabilities
Soft microprocessor gains RTOS support
Extreme FPGAs gain Serial RapidIO support
Programmable logic devices pass automotive test
Low cost FPGAs turn to display interfacing
Programmable power manager costs less than a buck
Low-cost FPGAs embed high-speed serdes I/O
Soft microprocessor is optimised for Lattice FPGAs
FPGA and IP combine to master SPI-4.2
Programmable logic gurus go online with blogs
Lattice FPGA IP support expands
Programmable clocks suit smaller systems
IP cores are tailored for top-performing FPGAs
System chip FPGAs gain PCI Express support
Programmable logic meets automotive standard
FPGA family takes on more system functions
FPGAs upgrade economical processing
FPGAs exploit advantages of 90nm Fujitsu process
Danish consultant joins design programme
Crossover programmable logic fills the gap
In-system-programmable clocks add more features
Close relationship provides speedy tool support
Design services company chooses LatticeXP FPGA
Programmable logic design tool suite is enhanced
Power manager devices provide precise monitoring
FPGAs host low-cost PCI Express interface
Mugford to bring fresh approach
Nonvolatile FPGAs sleep on the job to save energy
Microcontroller core is made for FPGA applications
PLDs cross over into FPGA applications
Design services programme formalises partnerships
Software reconfigures FPGAs on the fly
IP cores are ready to run on latest FPGA family
Upgrade for free programmable logic software
Programmable logic design tools upgraded
Alliance aims to enhance FPGA performance
Basestation conference showcase for FPGAs
FPGA design delivers high-speed channel correction
Novel architecture cuts cost of nonvolatile FPGAs
Programmable power manager handles lower voltages
Free tools to start on programmable logic design
RTL synthesis upgrades FPGA design software
Programmable chip suits Pirelli's platform
Tool suite boasts faster FPGA design
Expanded PLD enables digital display extender
Lead free packaging gains in popularity
Award for programmable clock devices
Core library supports latest economy FPGAs
Low-cost FPGAs hit production on schedule
Mentor deal extends tool offerings
Lattice invests in Fujitsu's new fab
Economy FPGAs gain CAN and FireWire IP support
Programmable system chips take Sonet onboard
Programmable system chip meets basestation specs
New architecture brings economy and DSP to FPGAs
Power manager simplifies analogue design at Thales
Upgrade for programmable logic design tools
CPLD works as ideal AMD coprocessor
Frugal CPLDs gain more macrocells
ASIC and FPGA come together to optimise SPI4.2
Approved cores speed programmable system design
In-system programmable PLD runs to 1024 macrocells
Programmable power manager scoops French award
Backplane transceivers pass the test
Serdes transceiver cuts 10Gbit/s power budget
Field programmable system chip aids optical nets
Power management standardisation across PCBs
Briefcase shows off serial data analysers
Programmable chip includes four serdes channels
Programmable interface is key to optical Ethernet
Programmable designs keep track of revisions
World's fastest and smallest claims for PLD
Tools support novel programmable power managers
Ethernet over Sonet solution enables multiplexer
In-system programmable devices come to handhelds
Chip combination speeds Sonet backplanes
FPSC device enables smarter networking
Transceiver rips data across backplanes
Programmable logic stretches to automotive specs
The simple machine for complex design
MSC gains further Lattice coverage
Lattice to acquire Cerdelinx Technologies
Infinitely reconfigurable FPGAs are instantly on
Novel PLD trades logic and memory functions
Complex logic range goes even wider
Complex programmable logic covers lower voltages
The simple machine for complex design
Speedy 5ns performance from 768-cell CPLD
In-system programming software meets the standard
In-system reprogrammable 5th-order lowpass filter
Lattice acquires Agere's FPGA business
Software programs analogue devices
Analogue front end is dynamically reconfigurable
Lattice and Altera finally bury the hatchet
I2P acquisition is intellectual boost to Lattice
Big, fast and wide PLDs in full production
