Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispLSI 2000VE family
Edited by the Electronicstalk Editorial
Team on 23 March 2001
Big, fast and wide PLDs in full
production
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family.
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family The 3.3V in-system programmable (ISP) Complex PLD (CPLD) family comprises five devices, and offers logic densities from 32 to 192 macrocells and features Lattice's pace setting SuperFAST architecture
This article was originally published on Electronicstalk on 5 Nov 2001 at 8.00am (UK)
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Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
The fastest device, the ispLSI 2032VE, raises the PLD speed-bar to 300MHz with 3ns pin-to-pin speeds, the fastest PLD in the industry.
As requirements for higher system clock frequencies increase, faster registered logic timings become critically important.
The second-generation ispLSI 2000VE devices also feature the fastest registered I/O timings of any 3.3V CPLDs, with input-to-clock setup times of 2.0ns and clock-to-output delays of 2.0ns.
Further reading
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
In-system reprogrammable 5th-order lowpass filter
Lattice Semiconductor has added to its ispPAC programmable analogue device family with the ispPAC81 in-system programmable continuous time filter.
These latest specifications equate to performance approximately one-third faster than the closest 3.3V competition.
Using advanced submicron E2CMOS silicon technology, the performance of these 3.3V second-generation BFW devices will eliminate critical system performance bottlenecks.
The entire ispLSI 2000VE family offers a complete line of board-space saving packages, from traditional plastic leaded chip carriers (PLCC) and plastic/thin quad flat packs (PQFP/TQFP) to advanced fine-pitch ball grid arrays (fpBGA).
Fine pitch BGA package options available for selected ispLSI 2000VE devices reduce required PCB space dramatically.
For example, PCB space savings can be as much as 45% when using the 1.0mm ball pitch fpBGA package for the ispLSI 2128VE when compared with a more traditional TQFP package option.
There are five members in the ispLSI 2000VE family.
The fastest device, the ispLSI 2032VE, clocks in with 300MHz/3ns performance.
The second member, the ispLSI 2064VE, is available in 32 and 64 I/O options and delivers 280MHz/3.5ns speed.
The third member, the ispLSI 2096VE, provides 250MHz/4ns performance.
The fourth member, the ispLSI 2128VE, offers the most I/O pins in the family with 64 and 128 I/O options available, while operating at 250MHz/4ns.
The ispLSI 2192VE is the fifth member and offers the highest macrocell count of the family (192) together with 225MHz/4ns system performance.
The ispLSI 2000VE family of devices is supported in Version 8.2 of Lattice's ispDesignEXPERT logic fitter, which supports logic design implementation with all leading CAE design tools.
Prices in high volume range from less than $2.00 for the 32 macrocell device (ispLSI 2032VE) to less than $7.00 for the 192 macrocell device (ispLSI 2192VE).
All are available now.
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