Analogue front end is dynamically reconfigurable

Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.

Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.

The company claims its ispPAC30 is the industry's first high performance in-system programmable and dynamically reconfigurable analogue IC.

The ispPAC30 device integrates all the essential analogue front-end functions for a typical data acquisition/conversion application.

It brings superior flexibility through the new capability of dynamic in-system reconfiguration of gain, analogue routing, precision voltage reference, output amplifier configuration, I/O, and other features, coupled with an enhanced architecture and increased bandwidth of operation - up to 1.5MHz.

With its superior performance capabilities, the ispPAC30 device is an ideal companion for a single or dual A/D convertor.

"It's always been tough to design flexible systems around fixed function analogue circuits", said Andy Robin, VP of New Venture Business for Lattice.

"Now the dynamic in-system reconfiguration capability of the ispPAC30 opens new doors for engineers by enabling implementation of ultra-flexible analogue circuits with high precision".

The ispPAC30 device provides all typical signal-conditioning functions for a data acquisition application, such as programmable gain, offset, and filtering.

The rail-to-rail output swing, along with very fine gain resolution (0.01x steps) and an offset adjustment capability makes this device suitable for multichannel signal conditioning and many control applications.

Power sensitive applications can also take advantage of the ispPAC30's 10mA standby current.

ispPAC30 designs can be implemented using Lattice's popular PAC-Designer version 1.3 software.

PAC-Designer software is an intuitive schematic design entry and simulation tool.

A new capability introduced in this latest version (PAC-Designer v1.3) is manufacturing support library functions.

These functions can be used to automatically calibrate the analogue parameters of the circuit in the manufacturing line to compensate for other components' tolerances, resulting in higher performance and yield of the end product at much reduced time and cost.

PAC-Designer Version 1.3 (isppac.exe) is available for free download from www.latticesemi.com.

The PACsystem30 is a low cost development tool designed to enable designers to build quick prototypes of their circuit implementation and to measure its performance.

The design implemented using PAC-Designer is downloaded into the device through the ispDownload cable that connects to the PC's parallel port.

The PACsystem30 is comprised of an evaluation board for the ispPAC30, an ispDownload cable, ispPAC Handbook, PAC-Designer v1.3 softwar, and two - ispPAC30-01PI samples.

The ispPAC30 device in industrial temperature grade (-40 to +85C) is priced under $7 per device in thousands.

The ispPAC30 device is available in both 24-pin SOIC and 28-pin DIP packages.

The ordering part numbers of the devices in these two packages are ispPAC30-01SI and ispPAC30-01PI, respectively.

PACsystem30 evaluation kits are also available through authorised Lattice Semiconductor distributors or on the Lattice Semiconductor website at a suggested retail price of $149.

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