Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispMACH 51024VG
Edited by the Electronicstalk Editorial
Team on 20 November 2001
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG This in-system programmable (ISP) logic family, which provides double the logic capacity of the popular ispLSI 5000VE family, includes new features such as advanced I/O standard sysIO support and sysCLOCK phase locked loops (PLLs) to meet next generation system design needs
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Performance for the first device, the ispMACH 51024VG, is specified at 5ns pin-to-pin logic delays (tPD) with an operating frequency (fMAX) of 178MHz, world-class performance for a device of this density.
The release of this family represents the completion of Lattice's second generation of BFW (big-fast-wide) products, consisting of the 3.3V power supply ispMACH 5000VG, ispLSI 2000VE and ispLSI 5000VE families.
"The ispMACH 5000VG is the result of extensive collaboration between Lattice's silicon and software designers", said Stan Kopec, Vice President of Corporate Marketing at Lattice.
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"It represents a new class of SuperBIG CPLD with system-level integration and features that still provides traditional CPLD ease-of-design, performance and nonvolatile, 'instant-on' capability".
The devices from the ispMACH 5000VG family incorporate a SuperWIDE macrocell architecture pioneered in Lattice's ispLSI 5000V family.
Logic capacities beginning at 768 macrocells are large enough to hold multiple functions commonly implemented in CPLDs such as bus bridges, memory controllers, and control logic.
The large number of sysIO-capable pins (from 192 to 384 per device) provided in the ispMACH 5000VG devices makes them ideal for wide bus interface applications.
The instant power-up capability of these devices makes them suitable for power-up sequence control in large, complex systems.
Each I/O pin on the ispMACH 5000VG devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces.
General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 and 1.8V).
The LVTTL and LVCMOS 3.3 interfaces are 5V tolerant, supporting easy integration into legacy designs.
Programmable drive levels for these standards facilitate the elimination of series termination resistors, reducing overall system cost.
Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support.
The ispMACH 5000VG family also supports GTL+, PCI, and PCI-X I/O configurations for use in high-speed bus interfaces.
The ispMACH 5000VG devices have two sysCLOCK PLLs that provide precise timing control for today's high-speed designs.
Designers can generate complex clock waveforms with the clock multiply and divide capability of the PLL as well as adjust setup, hold and clock to output timings by shifting the clock under sysCLOCK control.
This family uses the proven SuperWIDE 68-input logic block that is found in other ispLSI 5000 devices, providing excellent support for emerging 64bit applications.
Lattice has found that for complex functions this SuperWIDE capability leads to a 60% performance gain compared to devices with the more traditional 36-input logic block.
Additionally, Lattice enhanced the ispMACH 5000VG logic block by increasing the maximum number of product terms per function from the 35 implemented in the ispLSI 5000VE series to 160.
This leads to further performance improvements, up to 25% faster than architectures that support a maximum of 35 product terms per function.
The ispMACH 5000VG family is supported by Lattice's new ispLEVER Version 1.0 design tools.
The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispMACH 5000VG devices while maximising resource utilisation.
This is achieved through timing driven placement and routing coupled with optimised synthesis support from vendors such as Exemplar and Synplicity.
Lattice customers with valid software maintenance agreements will be upgraded to the new software suite during the first quarter of 2002.
The ispMACH 51024VG is available now in 484- and 676-ball fine pitch ball grid array (BGA) packaging featuring a space-saving 1mm ball pitch.
Projected pricing for the ispMACH 51024VG is as low as $50.00 in high-volume for the second half of 2002.
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