Product category:
Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: ispLever
Edited by the Electronicstalk Editorial
Team on 24 April 2002
The simple machine for complex design
"The simple machine for complex design" is the description given by Lattice Semiconductor to its next-generation ispLever design tools.
"The simple machine for complex design" is the description given by Lattice Semiconductor to its next-generation ispLever design tools The ispLever tools, fully integrated with leading CAE synthesis and simulation tools, are designed to provide powerful new capabilities and easy to use features in a single design flow supporting Lattice ispMACH, ispLSI, ispGDX, ispGAL and GAL devices, including the revolutionary new ispMACH 5000VG and ispMACH 4000 CPLD device families
This article was originally published on Electronicstalk on 18 Sep 2002 at 8.00am (UK)
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The simple machine for complex design
Dubbed "The simple machine for complex design", the latest generation of the ispLever design tool provides developers a simple powerful tool to use with all of Lattice's programmable logic products.
Programmable designs keep track of revisions
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite.
The ispLever system builds on the powerful project navigator used in Lattice's ispDesignExpert tools, with enhancements to the GUI to support new features and device families.
Lattice has also added a completely new constraints editor with multiple entry options and enhanced functionality.
The constraints editor allows the user to add pin and signal attributes, including selection of Lattice's new sysIO advanced I/O standards, to any pin quickly and easily.
Further reading
Approved cores speed programmable system design
The ispLeverCore Connection marks a new level of collaboration between Lattice and independent developers of intellectual property.
Upgrade for programmable logic design tools
The latest version of the ispLever design tool suite includes major upgrades in performance and features for the design of in-system programmable FPGA, CPLD and ispGDX devices.
Core library supports latest economy FPGAs
Lattice Semiconductor has released a number of key ispLeverCore intellectual property (IP) modules for its recently announced LatticeECP-DSP and LatticeEC FPGAs.
A graphical pin editor is included so users can simply drag-and-drop from an automatically generated signal list to a selected device package pin.
The ispLever Performance Analyst with SpeedSearch, familiar to ispMACH and MACH device users, has been enhanced to support static timing analysis for all Lattice device families.
Performance Analyst gives the user complete flexibility to select and evaluate any speed grade of a device without design recompilation.
It supports fast, detailed analysis of operating frequency, logic delay, clock-to-output delay, and input set-up time, as well as other critical timings at the click of a button.
With Lattice's revolutionary SpeedSearch capability, timing analysis results may be detailed and analysed with a minimum of effort.
The ispLever fitter is tuned to take full advantage of Lattice's many architectural innovations and includes global timing driven design for highest performance in a push button flow.
With the ispExplorer tool, users can easily set up multiple compiler runs using a variety of compiler settings through a graphical interface.
This unique feature provides users with a powerful tool for finding the optimum design compiler settings quickly by allowing them to view the results of multiple compilation runs in a straightforward spreadsheet-like table.
This allows the user to quickly select the settings that give the best results as the design evolves.
The user's standard internet browser has also been added to the Lattice tools arsenal by providing the facility for both HTML-based report viewing and navigation and the latest innovation from Lattice, ispUpdate.
The ispUpdate feature allows the user to query the Lattice website for the latest software enhancements and device support at any time and to download new support instantly via the Internet.
Lattice continues to lead all PLD suppliers by integrating and supplying industry leading synthesis and simulation tools from Mentor Graphics and Synplicity.
The ispLever tools support both Leonardo Spectrum and Synplify VHDL and Verilog synthesis tools and the ModelSim RTL and Timing Simulation tool.
To complete the design flow, Lattice's ispVM System is integrated with the ispLever design tool.
This highly efficient programming software interface includes device programming support for all Lattice ISP devices and includes JEDEC, SVF, and full support for the IEEE1532 ISC programming standard.
Lattice's ispLever design tools are designed to extract the highest performance and usage from the industry's most diverse and powerful portfolio of in-system programmable logic devices.
The ispLever system has been thoughtfully designed as the platform for future Lattice programmable design flows as well.
The ispLever design tools will also support Lattice's recently purchased Orca-Foundry FPGA and FPSC design tools in a future release.
The ispLever design tools are available for immediately shipment starting at $995 list price.
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