Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispMACH 4000V
Edited by the Electronicstalk Editorial
Team on 17 May 2002
Complex programmable logic covers lower
voltages
Available now from Lattice Semiconductor, the ispMACH 4000V family is a 3.3V series of ispMACH 4000 SuperFAST ISP CPLDs.
Available now from Lattice Semiconductor, the ispMACH 4000V family is a 3.3V series of ispMACH 4000 SuperFAST ISP CPLDs In addition to releasing all densities of the ispMACH 4000V family, Lattice has also released the final members of its industry-leading 2.5 and 1.8V ispMACH 4000B and ispMACH 4000C families
This article was originally published on Electronicstalk on 25 Sep 2002 at 8.00am (UK)
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Lattice is now in volume production with 32-, 64-, 128-, 256-, 384- and 512-macrocell versions of all three families.
The ispMACH 4000 devices couple industry-leading performance of up to 380MHz and 2.5ns pin-to-pin logic delay with the lowest dynamic power consumption available while supporting I/O standards between 3.3 and 1.8V.
In addition to providing the industry's first fully production released 1.8V in-system programmable CPLDs, Lattice now bridges multiple supply voltage generations by offering the same product architecture and leadership performance specifications with 1.8, 2.5 and 3.3V supply voltage options.
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These three ispMACH 4000 families represent the continued expansion of Lattice's third generation of big, fast and wide (BFW III) products and are a generation ahead of the competitive CPLD offerings in the marketplace today.
"This single CPLD architecture, available in three core voltages, with mainstream logic densities, industry-leading performance and lowest active power, provides system designers with a one-stop solution for CPLD design", said Stan Kopec, Vice-President of Marketing.
"This family extends Lattice's leadership position in CPLD solutions".
The ispMACH 4000 product line provides logic designers with a single architecture that covers a wide range of logic capacities, with 6 logic density options from 32 to 512 macrocells in a variety of advanced package and I/O options.
I/O counts range from 30 to 208 across the family.
The devices provide optimal logic implementation for many glue logic, state machine, decoder, bridging, power-up and signal handshaking functions.
These functions are critical for the implementation of many high performance computing, communications and industrial applications.
At 32 macrocells, the ispMACH 4032, provides 2.5ns pin-to-pin delay, 2.2ns clock-to-output delay, 1.8ns setup time and 380MHz operating frequencies - 25% faster than available competing devices.
At 512 macrocells, the ispMACH 4512, provides 3.5ns pin-to-pin delay, 3.0ns clock-to-output delay, 2.2ns setup time and 300MHz operating frequencies - 58% faster than available competing devices.
Lattice's SuperFast devices outperform the competition across all logic density points.
Traditionally, low power consumption has been an important issue only for designers of equipment with limited available power, a small percentage of total PLD applications.
However, designers of high performance computing and communications systems, which traditionally have had relatively unlimited power budgets, are increasingly interested in lowering power consumption to reduce operating cost and enhance system reliability.
Lattice designed the ispMACH 4000 family to provide the best performance available, coupled with significantly lower power for these mainstream PLD applications.
Digital design techniques, coupled with the use of low power non-volatile cells, allows static current to be reduced to as low as 1.3mA.
The use of a 1.8V core provides reduced dynamic power consumption for the family.
As a result, the ispMACH 4256 device typically dissipates 78% less power at 100MHz than other commercially available 2.5V CPLD solutions.
The ispMACH 4000 devices have two I/O banks, each with their own power supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3, 2.5 and 1.8V outputs.
Device input buffers have programmable thresholds that support the above standards independent of the I/O bank voltage.
This approach, coupled with the availability of 3.3, 2.5 and 1.8V devices, gives designers the flexibility needed in today's multiple-voltage environments.
All ispMACH 4000 devices are also boundary scan testable (IEEE1149.1) and in-system programmable through an IEEE1532-compliant JTAG boundary scan interface.
The ispMACH 4000 product line is supported by Lattice's new ispLEVER design tools.
The ispLEVER tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance of the ispMACH 4000 devices while maximising resource utilisation.
This is achieved through timing driven placement and routing coupled with optimised synthesis support from vendors such as Exemplar and Synplicity.
Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export.
The ispLEVER software is available in PC as well as Unix workstation versions.
All devices in the ispMACH 4000V/B/C families are available now.
Packages offered include 44-TQFP, 48-TQFP, 100-TQFP, 128-TQFP, 176-TQFP and 256-ball fine pitch BGA.
For high-volume applications, pricing for the 1.8V ispMACH 4032C is projected to be less than $1.00, whereas the ispMACH 4512C will be priced below $15.00.
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