Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispMACH 5256B
Edited by the Electronicstalk Editorial
Team on 10 June 2002
Complex logic range goes even wider
Lattice Semiconductor has released the first member of its 2.5V ispMACH 5000B family, the 256-macrocell ispMACH 5256B.
Lattice Semiconductor has released the first member of its 2.5V ispMACH 5000B family, the 256-macrocell ispMACH 5256B The introduction of this family continues Lattice's rollout of its 3rd-generation BFW (big-fast-wide) complex PLD products
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The ispMACH 5256B device is the first of four ispMACH 5000B devices which span logic capacities from 128 to 512 macrocells and offer performance as fast as 3.5ns tPD (pin-to-pin logic delay) and operating frequencies to 275MHz for the fastest family members.
Advanced process technology enables the ispMACH 5000B to provide high-speed performance and 2.5V power supply operation.
Programmable sysIO interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL etc) support.
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For the ispMACH 5256B, pin-to-pin delays as fast as 4.0ns and operating frequencies up to 250MHz are supported.
SuperWide (68-input, 32-macrocell) logic blocks efficiently implement wide logic functions such as those found in advanced 32 and 64bit systems.
The ispMACH 5000B family provides logic designers with a single architecture to meet a broad range of system requirements.
The family includes multiple logic densities (128, 256, 384, and 512 macrocells) in a variety of advanced package and I/O options.
The wide range of sysIO-capable pins (from 92 to 256 per device) provided in the ispMACH 5000B devices makes them ideal for wide bus interface and memory interface applications.
The instant power-up capability of these devices makes them suitable for critical power-up sequence control in complex systems.
"The ispMACH 5000B family leverages the popular 5000 series SuperWide CPLD architecture and delivers a high performance, 2.5V solution that supports the advanced I/O interface standards required for today's complex system designs", said Steve Stark, Director of Product Marketing at Lattice.
Each I/O pin on the ispMACH 5000B devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces.
General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8V).
Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost.
Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support.
The ispMACH 5000B family also supports GTL+ and PCI I/O configurations for use in high-speed bus interfaces.
The new family uses Lattice's industry-leading SuperWide 68-input logic block employed in earlier 3.3V ispLSI 5000VE and ispMACH 5000VG families.
The SuperWide architecture, the widest available in any CPLD, provides excellent support for next-generation 64bit applications.
This SuperWide capability can deliver a 60% performance gain for complex logic functions when compared to traditional CPLD devices using 36-input logic blocks.
The ispMACH 5000B family is supported by Lattice's new ispLever design tools.
The ispLever tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispMACH 5000B devices while maximising resource usage.
This is achieved through timing driven placement and routing coupled with optimised synthesis support from vendors such as Mentor Graphics and Synplicity.
Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export.
The ispLever software is available in PC as well as Unix workstation versions.
The ispLever design tools, including Synplicity's Synplify VHDL and Verilog synthesis tools, are available for download from the Lattice website.
These full-featured tools are designed to provide users easy access to the innovation and high performance of the ispMACH 5000B family architecture.
The ispMACH 5256B is available now in 128-pin TQFP, 208-pin PQFP and 256-ball fine-pitch BGA packages.
The fpBGA package features a space-saving 1mm solder ball pitch.
The ispMACH 5000B family also supports system designers' needs for density migration within a common package/pinout footprint.
As a result, designers are able to shrink or expand their designs across multiple logic macrocell density options while maintaining the same printed circuit board layout.
The balance of the ispMACH 5000B devices are expected to be released in the third quarter of 2002.
Projected pricing for the ispMACH 5256B is as low as $8.00 in high-volume.
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