Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispXPGA
Edited by the Electronicstalk Editorial
Team on 17 July 2002
Infinitely reconfigurable FPGAs are
instantly on
The ispXPGA (in-system programmable expanded programmable gate array) family combines on-chip E2 memory with SRAM cells in a nonvolatile architecture that allows infinite reconfiguration.
Lattice Semiconductor has developed the industry's first in-system-programmable and dynamically reconfigurable instant-on FPGA family The ispXPGA (in-system programmable expanded programmable gate array) family combines on-chip E2 memory with SRAM cells in a nonvolatile architecture that allows infinite reconfiguration
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Analogue front end is dynamically reconfigurable
Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.
This unique marriage of technologies is named ispXP, for expanded programmability.
As the ispXP devices in the ispXPGA family self-configure in microseconds at power-up ("instant on"), they are available to an electronic system during its power-up sequence.
The products are highly secure, as well, as on-chip E2 memory means no external bit stream is exposed during configuration, and security bits can inhibit FPGA pattern readback.
Further reading
Software programs analogue devices
Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
In-system reprogrammable 5th-order lowpass filter
Lattice Semiconductor has added to its ispPAC programmable analogue device family with the ispPAC81 in-system programmable continuous time filter.
The family is supported in Lattice's ispLever integrated, hierarchical CPLD/FPGA design software.
"Lattice is excited to bring innovative programming technology to the FPGA market with a complete, mainstream product offering", said Steven A Laub, Lattice's President.
"Our unique value for customers with our nonvolatile/infinitely-reconfigurable/instant-on approach overcomes the deficiencies of conventional SRAM FPGAs".
The features most sought by users in an FPGA are all built into the ispXPGA family.
These include: a versatile PFU (programmable function unit); hardware-accelerated arithmetic and muxing to enhance performance; distributed single-port, dual-port, FIFO, and shift-register memory for local scratchpad needs; wide-gating expansion for operations with up to 20 inputs; two flip-flops per lookup table improve efficiency/speed of library elements, pipelining, and register-retiming for boosting operating frequency; sysMEM embedded 4Kbit memory blocks; single-port, dual-port, and FIFO configurations; parity provided for with x9 and x18 support; Variable-Length-Interconnect optimised for performance and efficiency; sysIO input/outputs giving the user a choice of dozens of I/O types for single-ended and differential needs meeting industry standards for varied applications; sysClock phase-locked-loops (PLLs); clock frequency synthesis; multiple clock generation; clock alignment at either board or device level; programmable delay for fine-tuning of clock signals in 250ps increments; sysHSI (high-speed interface) 850Mbit I/Os with serdes and clock recovery for handling ultra-fast data streams; and 1.8, 2.5 or 3.3V operation.
The ispXPGA family covers 125K gates to 1.2M gates or 2K to 15K logic elements.
Gates are counted using the industry-standard approach.
Block RAM goes from 92 to 414Kbit, while distributed RAM reaches from 30 to 246Kbit.
The family has products from 160 to 496 I/Os, including four to 20 sysHSI clock pairs.
This range of resources addresses the vast majority of customer design needs.
The ispXPGA family is complemented by Lattice's new ispXPLD family, also with ispXP.
Release 2.0 of the Lattice ispLever design software includes complete support for the ispXPGA and ispXPLD families, as well as Orca field programmable system chips (FPSC), ispMACH CPLDs, ispGDX crosspoint switches, and ispGAL SPLDs.
Tools added to ispLever for the ispXPGA family include a floorplanner, timing-driven place and route, a module compiler, core manager, enhanced constraint editor, and expanded timing analysis, plus HTML report browsing.
The overall user interface of the ispLever software carries on from prior releases.
This maintains the design environment customers are familiar with, and avoids unnecessary new learning.
This means customers can get started quickly with v2.0.
Users' preferred HDL design flows are provided for through Lattice's relationship with major EDA tool suppliers.
HDL synthesis support is available for Exemplar Leonardo Spectrum, Mentor Design Architect, Synopsys Design Compiler, and Synplicity Synplify.
Simulation support is available for Cadence Verilog-XL; Mentor ModelSim, QuickSim, and QuickVHDL; Synopsys VSS and Chronologic; Viewlogic ViewSim; and multiple sources of VHDL/Vital.
Board-level verification support is available for Mentor/Telalogic Tau, Synopsys PrimeTime, and Viewlogic Blast.
Lattice has developed in-house LeverCore IP cores for its customers.
These cores are aimed at bus, communications, memory, and DSP applications.
They are parameterised so users can get the core functionality they desire.
Initial cores include: PCI master/target and target 64bit/66MHz; Utopia Level 3 ATM and PHY receive and transmit; POS PHY Level 3 link and physical layer interfaces; a multichannel DMA controller; DDR SDRAM controller; loadable parallel and serial FIR filters; and a Reed-Solomon encoder.
More Lattice LeverCore IP cores are in development now.
All LeverCores comply with the Reuse Methodology Manual HDL code development guidelines to maximise their usefulness to our customers.
LeverCores include testbenches and extensive documentation.
The initial ispXPGA device to be offered is the 1.2 million gate product, which is called the LFX1200 (Lattice, FPGA product line, ispXPGA family, 1200K gates).
It is being made available in commercial (0 to 70C) and industrial (-40 to +85C) temperature grades as well as 1.8V and 2.5/3.3V power supply versions.
Samples will be available later in Q3 with production in Q4.
It comes in a 900-ball fine-pitch BGA package or a 680-ball thermally enhanced fine-pitch BGA package.
The LFX1200 is priced at $345 per device in thousands.
ispLever design software v2.0 is available for customers to begin designs now.
It will also be available in a full-function get-started version on the free Lattice Starter CD.
Lattice LeverCore IP cores will be available in free trial versions from the company's website.
These trial versions are encrypted and can be simulated with the rest of a customer design.
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