Novel PLD trades logic and memory functions

The ispXPLD (in-system programmable expanded PLD) architecture is the first PLD architecture to allows users to efficiently trade-off fast logic and block memory resources.

The ispXPLD (in-system programmable expanded PLD) architecture is the first PLD architecture to allows users to efficiently trade-off fast logic and block memory resources.

The novel architecture allows each multifunction block (MFB) to be used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16Kbit per MFB), yielding up to 1024 macrocells or 512Kbit of memory on a single device, equivalent to 300K system gates.

The SuperWide architecture also supports functions of up to 136 inputs in a single level of logic, doubling the fan-in of any other PLD family and providing fast support for extremely wide buses and logic functions.

Performance of up to 285MHz, with pin-to-pin logic delay of 3.5ns and clock-to-output delay of 2.5ns is specified.

The ispXPLD family also uses Lattice's new ispXP (ISP expanded programming) technology that combines the traditional product-term based PLD benefit of "instant-on", nonvolatile programming together with real time, unlimited reconfigurability found in SRAM-based FPGAs.

"This breakthrough architecture provides a convergence of device architecture and programming technology that will allow ispXPLDs to crossover traditional programmable logic segment boundaries", stated Steven A Laub, President of Lattice Semiconductor.

"We now have devices that combine the speed, predictability and nonvolatility of CPLDs together with the system-level features, density and reconfigurability of FPGAs.

System designers will no longer have to compromise one for the other.

As such, Lattice XPLDs signal the start of a third wave of PLDs, destined to succeed its simple PLD and complex PLD predecessors".

The initial series of ispXPLD devices, the ispXPLD 5000MX family, will be available in 1.8, 2.5 and 3.3V power supply versions, designated the 5000MC, 5000MB and 5000MV series.

The devices will be offered in 256, 512, 768 and 1024 macrocell-equivalent densities with 141 to 381 user I/O, corresponding to 75K to 300K system gates.

The first device, the ispXPLD 5512MX, packaged in a 484 fine pitch BGA (fpBGA) package, will sample shortly.

Programmable sysIO interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, LVDS, etc.) support.

Advanced silicon technology, combined with proprietary circuit design techniques, provides standby power consumption as low as 36mW per device for power-sensitive applications.

Each device also incorporates Lattice's sysClock PLL capability for high-performance on-chip clock synthesis.

The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously relegated only to FPGAs or ASICs.

Potential application areas include high-performance bus bridges, intelligent backplane interfaces, protocol processors and the like.

The homogeneous ispXPLD architecture consists of a number of uniform Multi-Function Blocks interconnected by a single-level, high speed programmable Global Routing Pool (GRP).

The GRP also connects the MFBs to the I/O cells.

Devices in the ispXPLD 5000MX family integrate from 8 to 32 MFBs into a single device.

Each MFB within an ispXPLD device can be programmed independently to implement 32 macrocells of SuperWide logic, an 8Kbit dual-port RAM, a 16Kbit single-port RAM or FIFO, or a 128 x 48bit content addressable memory (CAM).

Dedicated FIFO control logic is included on-chip so programmable resources are not consumed providing these memory control functions.

While the basic logic block configuration supports up to 68 logic inputs in a single level of logic, cascading MFBs allows the devices to support functions of up to 136 inputs without incurring an additional level of logic delay, further raising the bar for a wide logic architecture.

Each I/O pin on the devices can be configured to support high-speed memory interfaces, advanced bus standards, or general-purpose interfaces.

General-purpose interface support includes LVTTL or LVCMOS (3.3, 2.5 or 1.8V).

Four independent I/O banks provide support for multiple interface voltages and standards on a single device.

Programmable drive levels for these standards facilitate the elimination of series termination resistors, further reducing overall system cost.

Interface to high speed DRAMs, SRAMs, and other high performance memory devices is made possible with SSTL2, SSTL3, and HSTL I/O support.

The family also supports GTL+, PCI, LVDS and LVPECL I/O configurations for use in high-speed bus interfaces.

The ispXPLD devices have two sysClock PLLs that provide precise timing control for today's high-speed designs.

Designers can generate complex clock waveforms with the clock multiply and divide capability of the phase-locked loops, as well as adjust setup, hold and clock to output timings by shifting the clock under sysClock control.

Lattice's new ispXP technology enables its ispXPLD family to combine programmability benefits found in both non-volatile PLDs based on electrically erasable technology as well as reconfigurable FPGAs based on SRAM technology.

As a result, the devices feature: "instant on" operation at system startup, allowing them to support critical system "heartbeat" functions without external initialisation; nonvolatile in-system programming, thereby giving higher integration through the elimination of an external boot PROM; enhanced design security as programming bit streams are invisible at system initialisation; and infinite reconfigurability via an 8bit microprocessor port or JTAG boundary scan port for the ultimate in system adaptability.

The ispXPLD 5000MX family is supported by Lattice's new ispLever v2.0 design tools.

The ispLever tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispXPLD devices while maximising resource usage.

This is achieved through timing driven placement and routing coupled with optimised synthesis support from vendors such as Mentor Graphics/Exemplar and Synplicity.

Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export.

The ispLever software is available in PC as well as Unix workstation versions.

The ispLever design tools, including VHDL and Verilog synthesis tools, are available for download from the Lattice website.

The ispXPLD 5512MX in the 1.0mm ball pitch, 484 fine-pitch BGA package will sample later this quarter with initial production scheduled for Q4.

Pricing for the ispXPLD 5512MC in volumes of 1000 pieces start at $17.75.

Additional members of the ispXPLD 5000MX family are expected to be released over the coming year.

(This was Electronicstalk's Top Story on 16 July 2002).

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