Transceiver rips data across backplanes

Lattice Semiconductor has managed to get its ORT82G5 field programmable system chip (FPSC) to pass data error-free at 3.7Gbit/s across 66cm of FR-4 backplane.

Lattice Semiconductor has managed to get its ORT82G5 field programmable system chip (FPSC) to pass data error-free at 3.7Gbit/s across 66cm of FR-4 backplane, making it the industry's fastest programmable XAUI-compliant backplane transceiver in production.

"Lattice continues to deliver innovative solutions for high performance system-level design", said Stan Kopec, vice president of corporate marketing at Lattice.

"The ORT82G5 is our latest generation backplane FPSC, following our successful ORT4622 and ORT8850 devices.

These tests verify the superior speed and flexibility of our solution.

Backplane applications, especially XAUI and Fibre-Channel, are a perfect fit for the ORT82G5.

The eight independent, full-duplex serialiser-deserialiser (serdes) cores are best-in-class with 3.7Gbit/s bandwidth, and the programmable logic will allow system designers to interface to virtually any processor or framer", he added.

Lattice's FPSC devices are high-performance programmable devices that combine optimised embedded core functions together with flexible, general-purpose FPGA logic.

In addition to its eight serdes cores and 400K Orca FPGA gates, the ORT82G5 includes embedded XAUI and Fibre-Channel state machines, bypassable 8B/10B encoding/decoding support plus multichannel alignment capability without using any FPGA gates.

At 225mW per channel, the device offers designers the highest available bandwidth at very low power.

"By optimising the device's programmable amplitude and pre-emphasis settings, minimum power consumption can be realised with the ORT82G5 while maintaining the signal integrity needed for error-free operation.

This is the kind of tangible benefit Lattice's programmable approach offers system designers as they develop advanced communications systems", added Kopec.

The device also features 372 programmable user I/Os supporting a variety of advanced interface standards including HSTL, SSTL, GTL+ and others to facilitate easy interfacing.

Designers can use the ORT82G5 to aggregate disparate parallel I/O into high-speed serial streams.

For example, designers can build a 20Gbit/s bridge for 10Gbit/s Ethernet; the high-speed serdes interfaces contain dual-XAUI interfaces with configurable back-end interfaces such as XGMII implemented on the FPGA side.

The ORT82G5 can also be used to provide a full 10Gbit/s backplane data connection with protection between a line card and switch fabric.

Lattice has demonstrated the ORT82G5 in its own lab using a Tyco HM-Zd test setup.

The ORT82G5 can drive 2e7-1 PRBS data over at least 66cm of FR-4 at 3.7Gbit/s (25% pre-emphasis) error-free exceeding the XAUI specification of 3.125Gbit/s over 51cm of FR-4 backplane.

"Our production parts show significant data rate margin to XAUI requirements, even across 102cm of FR-4 backplane.

Moreover, the additional bandwidth margin enables backplane designers to perform high-speed chip-to-chip bit-blasting in addition to permitting additional out-of-band signalling across the XAUI links", commented Kopec.

To document the superior characteristics of its serdes technology, Lattice has also just released its new "Serdes handbook".

This handbook provides actual data on the typical eye diagrams, jitter, lock time, and other key operational aspects of the ORT82G5's serdes block.

It is available in electronic form on the Lattice website.

The ORT82G5-600LBGA SERDES transceiver is currently shipping.

The unit price in quantities of 10,000 is $195.

The device is supported by Lattice's ispLever v2.0 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.

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