Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ORSO82G5
Edited by the Electronicstalk Editorial
Team on 13 November 2002
Chip combination speeds Sonet backplanes
Lattice Semiconductor and Velio Communications have demonstrated complete interoperability between Velio's VC2002 and Lattice's ORSO82G5 programmable backplane field programmable system chip (FPSC).
Lattice Semiconductor and Velio Communications have demonstrated complete interoperability between Velio's VC2002 and Lattice's ORSO82G5 programmable backplane field programmable system chip (FPSC) The solution combines a Velio Zeus switch fabric for switching Sonet streams at the STS1 level and Lattice's new ORSO82G5 FPSC for interfacing to Sonet-based backplanes
This article was originally published on Electronicstalk on 7 Jul 2003 at 8.00am (UK)
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"The interoperability test between the Lattice Semiconductor FPSC ORSO82G5 and the Velio VC2002 STS1 grooming switch family has been very successful.
It proves the reliable and stable functionality of customer architectures using Velio and Lattice parts up to 56in of FR4 signal trace length", commented Bill Woodruff, vice president of marketing at Velio Communications.
"Lattice's ORSO82G5 FPSC technology allows our Zeus grooming switch to seamlessly interface with existing and emerging Sonet line cards, thus preserving the carrier's enormous investment made in Sonet-based systems", Woodruff concludes.
The Zeus switch (VC2002) is a 180Gbit/s throughput, 72 x 72 STS-48/STM-16 Sonet/SDH grooming switch, with STS-1/AU-3 granularity.
For STS-192 traffic, the Zeus switch is an 18 x 18 grooming switch (with 1:4 de-interleaving).
It allows each STS-1 component of each input stream to be directed to an arbitrary STS-1 slot in an arbitrary output stream.
In effect, it is a 3456 x 3456 STS-1 switch.
The Lattice ORSO82G5 FPSC offers a clockless high-speed serial interface for interdevice communication on a board or across a backplane.
The built-in clock recovery of the ORSO82G5 supports higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane.
The ORSO82G5 supports Sonet data scrambling and descrambling, streamlined Sonet framing, transport overhead handling, cell insertion and extraction, idle cell insertion/deletion, plus the programmable logic to provide high-speed datapath functionality.
The serdes technology in the VC2002 is based on Velio's industry-leading GigaCore serial I/O technology, which uses transmit pre-emphasis and receive equalisation to improve transmission signal integrity.
The VC2002 interfaces with the ORSO82G5 over dual sets of four CML streams at 2.488Gbit/s.
Its dual banks can be switched in a hitless fashion for error-free data protection.
The Lattice serdes is the same technology employed in its ORT82G5 FPSC, a backplane transceiver featuring 8b/10b coding for use in high-speed Ethernet applications.
The serdes macrocell on the ORSO82G5 features programmable datarates from 1.0 to 2.7Gbit/s, and includes transmit pre-emphasis (programmable) for improved receive data eye opening.
Test results confirm a high level of margin in the data eye opening at the receiving Lattice device.
A technical note discussing the interoperability results can be found on the Lattice website.
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