Product category:
Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: ispLever v3.0
Edited by the Electronicstalk Editorial
Team on 03 March 2003
Programmable designs keep track of
revisions
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite.
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite Lattice's ispLever development tools are designed to extract the highest performance and usage from the industry's broadest and most powerful portfolio of programmable logic devices, including Lattice's ispXPGA and Orca FPGAs, ispXPLD and ispMACH CPLDs, ispGDX programmable interface devices and ispGAL SPLD product families
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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With this release, Lattice's ispLever software continues to build on its reputation as "the simple machine for complex design" by providing run-time performance improvements, updated 3rd party tool support, expanded Lattice device support and key functional enhancements.
"In the past year, we've made significant improvements to nearly every aspect of our design tools", stated Stan Kopec, Lattice Vice President of Marketing, "The ispLever platform has proven to be extremely flexible and efficient, more than able to accommodate new features while retaining a familiar look and feel".
The new ispLever v3.0 software includes improvements in logic compilation run-time of up to 30% compared with earlier versions, a streamlined installation procedure, new IP and macro support, and further integration of the Orca FPGA design flow into the ispLever suite.
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Noteworthy enhancements in ispLever v3.0 also include an automated revision control system.
Revision control helps the designer keep track of multiple design revisions with a simple GUI hierarchical tree.
When revision control is enabled, every action initiated by the user is tracked and instantly displayed in a revision control tree.
The user can jump to any point in the tree with one click.
Branches of the revision control tree can be deleted if desired, and the entire revision control system can be toggled on/off at any point in the design process.
The ispLever v3.0 software supports timing checkpoints in the FPGA design process.
Timing checkpoints speed the FPGA design compilation process by automatically checking compilation results while the software is running.
If it appears the user-defined constraints will not be met, the user is alerted so the process can be stopped and changes made.
This increases the efficiency of the design cycle by reducing time spent compiling designs.
Other powerful features and tools in this release include: FPGA floorplanning and timing-driven place and route; a performance analyst with SpeedSearch; ispExplorer; and ispVM system programming software.
Lattice continues to lead all programmable logic suppliers by integrating and supplying industry leading synthesis and simulation tools from Mentor Graphics and Synplicity.
Lattice supplies Leonardo Spectrum and Synplify VHDL and Verilog synthesis tools and the ModelSim RTL and Timing Simulation tool integrated into a variety of its ispLever design solutions.
In addition, Lattice provides support for other leading third-party design tools such as Synopsys, Cadence, and others via an efficient EDIF netlist interface.
ispLever v3.0 includes updates for the latest versions of all these tools.
The ispLever development tools are available for PC (Windows NT, 2000, XP) and Unix (Solaris 2.8) operating systems, starting at $995 list price.
A trial version is available for download from the Lattice website, along with a free 6-month evaluation licence.
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