Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ORT42G5
Edited by the Electronicstalk Editorial
Team on 21 April 2003
Programmable chip includes four serdes
channels
The ORT42G5 is a field programmable system chip incorporating four serdes channels each running at 0.6 to 3.7Gbit/s.
The ORT42G5 is a field programmable system chip (FPSC) incorporating four serdes channels each running at 0.6 to 3.7Gbit/s, plus embedded 8b/10b encoding, XAUI and Fibre Channel link state machines and over 10,000 FPGA logic elements, all in a compact 484 fine-pitch BGA package The device is targeted at high speed chip-to-chip and backplane applications such as 10Gigabit Ethernet, 1Gigabit and 2Gigabit Fibre Channel, and 10Gigabit Fibre Channel for the rapidly expanding 10Gigabit storage area networking market
This article was originally published on Electronicstalk on 20 Aug 2004 at 8.00am (UK)
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"With the introduction of the ORT42G5, Lattice is extending its leadership position in the programmable SERDES market", said Stan Kopec, Vice President of Corporate Marketing at Lattice.
"Our portfolio of serdes-based devices is already the broadest in the industry, and the ORT42G5 offers a cost-effective device that will save designers board space and reduce trace routing and complexity.
We've packed 4 channels of the industry's fastest production serdes along with plenty of programmable logic for bridging and proprietary packet processing functions.
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The competition requires at least two chips to accomplish what we can do in a compact 23 x 23mm footprint", Kopec added.
Lattice's FPSC devices are high-performance programmable devices that combine optimised embedded core functions together with flexible, general-purpose FPGA logic.
In addition to its four serdes channels and over 10,000 Orca FPGA logic elements for general-purpose logic, the ORT42G5 includes fully embedded 8b/10b encoding, XAUI and Fibre Channel link state machines and multichannel alignment capabilities.
The serdes on the ORT42G5 includes numerous best-in-class features, such as: a 3.7-0.6Gbit/s operating range per channel; less than 225mW per channel worst case power drain at 3.125Gbit/s; the ability to drive 1m of FR-4 backplane at 3.125Gbit/s; and fast locking times with bit realignment at 300ns (938bit times at 3.125Gbit/s).
The device also features 204 programmable user I/Os supporting a variety of advanced interface standards including LVCMOS, LVTTL, LVDS, Bus-LVDS, LVPECL, HSTL, SSTL3/2, GTL, GTL+, ZBT and DDR to facilitate easy interfacing.
Another FPSC device in the Lattice backplane portfolio, the ORT82G5, offers eight channels of the same serdes core.
To document the superior characteristics of its serdes technology, Lattice has just released the second edition of its "Serdes handbook".
This handbook provides actual data on the typical eye diagrams, jitter, lock time, and other key operational aspects of the serdes technology used in the ORT42G5 and ORT82G5 FPSCs as well as information on its ORSO82G5, ORT8850, ispGDX2 and ispXPGA product families.
It is available in electronic form on the Lattice website.
The ORT42G5-484PBGAM FPSC is currently available with production quantities available Q3 2003.
Volume price the second half of 2004 in quantities of 10,000 is $80.00.
The device is supported by Lattice's ispLever v3.0 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.
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