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Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: XPIO 110GXS
Edited by the Electronicstalk Editorial Team on 26 June 2003

Serdes transceiver cuts 10Gbit/s power
budget

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The XPIO 110GXS is claimed to be the industry's lowest power 10Gbit/s serdes transceiver based on 0.13-micron CMOS technology.

The XPIO 110GXS is claimed to be the industry's lowest power 10Gbit/s serdes transceiver based on 0.13-micron CMOS technology Designed for Sonet OC-192 and 10 Gigabit Ethernet applications, the XPIO 110GXS consumes only 0.8W of power and supports optical transponder modules such as the 300-pin MSA as well as those for 10 Gigabit small form-factor pluggable (XFP) applications

The high-performance transceiver meets both Sonet and Ethernet jitter requirements.

"The addition of our first extended performance I/O device further demonstrates Lattice's leadership position in the serdes market", said Stan Kopec, Vice President of Corporate Marketing at Lattice Semiconductor.

"As the market leader in high-speed serdes-based programmable devices with our field programmable system chip (FPSC) product family, Lattice is fully committed to delivering the most complete portfolio of innovative FPGA and FPSC solutions at 10Gbit/s, and the XPIO 110GXS device is our next step towards achieving this objective".

Previous Lattice FPSC devices, such as the ORSO82G5 and ORT82G5, support 10Gbit/s traffic using four channels of 2.5 to 3.125Gbit/s serdes, depending on the encoding/decoding scheme utilised.

The new XPIO device generates and receives 10Gbit/s clock/data streams (full duplex) using CML signalling over a single channel, reducing the number of connections needed.

Offering a continuous operating range from 9.953 to 10.709Gbit/s, the low-power transceiver is ideally suited for Sonet OC-192 and 10 Gigabit Ethernet applications.

Lattice's new device can also be used in 200- or 300-pin MSA-based optical transponder modules.

The device supports 16:1 serialisation and 1:16 deserialisation with a parallel LVDS data range from 622 to 670Mbit/s supporting the Optical Internetworking Forum's SFI-4.1 and 10 Gigabit Ethernet's XSBI standards.

An on-chip low-jitter PLL generates all required clocks based on an external reference clock of 155.52 or 622.08MHz.

The integrated limiting amplifier further enhances design flexibility and improves the bit-error rate.

The device achieves its extremely low power consumption through a combination of advanced 0.13-micron CMOS technology, reduced 1.3V core and 2.5V I/O voltages, and proprietary circuit design techniques.

As a result, the devices typically consume only 0.8W when operating at 10Gbit/s, lower than any competitive transceivers currently available or announced.

Samples of the XPIO 110GXS device are available now, with volume production scheduled for the second half of 2003.

The device is packaged in an easy-to-use 15 x 15mm, 269-ball flip-chip BGA package.

Prices for the device are projected to start at $79.00 in 5000-piece quantities for delivery in the first half of 2004.

The ordering part number is XPIO 110GXS-01CF269C.

XPIO 110GXS evaluation kits are available through authorised Lattice distributors at a price of $4999.

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