Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispXPLD 51024MX and ispXPLD 5256MX
Edited by the Electronicstalk Editorial
Team on 15 August 2003
In-system programmable PLD runs to 1024
macrocells
Lattice Semiconductor has added of two new devices to its revolutionary in-system programmable expanded PLD family, the ispXPLD 51024MX and ispXPLD 5256MX devices.
Lattice Semiconductor has added of two new devices to its revolutionary in-system programmable expanded PLD family, the ispXPLD 51024MX and ispXPLD 5256MX devices The ispXPLD 51024MX features up to 1024 logic macrocells and up to 512Kbit of on-chip memory and represents the largest member of the family
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Big, fast and wide PLDs in full production
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family.
Analogue front end is dynamically reconfigurable
Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.
The ispXPLD 5256MX provides up to 256 logic macrocells and up to 128Kbit of on-chip memory and is the smallest member of the device family.
The ispXPLD architecture is the first PLD architecture that allows users to efficiently trade off fast logic and block memory resources.
The unique architecture offers multifunction blocks (MFBs) that can be independently used for logic functions (up to 32 macrocells per MFB) or memory functions (up to 16Kbit per MFB), yielding up to 1024 logic macrocells or 512Kbit of on-chip memory on a single device, equivalent to 300K system gates.
Further reading
Software programs analogue devices
Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
In-system reprogrammable 5th-order lowpass filter
Lattice Semiconductor has added to its ispPAC programmable analogue device family with the ispPAC81 in-system programmable continuous time filter.
The ispXPLD 51024MX device delivers 5.2ns pin-to-pin delay, 3.8ns clock-to-output delay, 3.0ns setup time and 235MHz operating frequencies.
The equivalent figures for the ispXPLD 5256MX device are 4.0ns, 2.8ns, 2.2ns and 300MHz, respectively.
The ispXPLD 5000MX family is available in 1.8, 2.5 and 3.3V power supply versions, designated the ispMACH 5000MC, 5000MB and 5000MV series, respectively.
The devices are offered in 256, 512, 768 and 1024 macrocell-equivalent densities with 141 to 381 user I/Os, corresponding to 75K to 300K system gates.
Programmable sysI/O interface capability provides flexible advanced I/O standard (GTL+, HSTL, SSTL, LVDS etc) support, as well as 5V-tolerant I/O.
Advanced nonvolatile E2CMOS silicon technology, combined with proprietary circuit design techniques, provides standby power consumption as low as 36mW per device for power-sensitive applications.
Each device also incorporates Lattice's sysClock phase-locked loop (PLL) capability for high-performance on-chip clock synthesis.
The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously served only by FPGAs or ASICs.
Potential application areas include high-performance bus bridges, intelligent backplane interfaces and protocol processors.
At 1024 macrocells, the ispMACH 51024MX is the highest density product-term-based logic architecture available in the industry, delivering wide decoding capability and predictability of timing.
With this new 1024 macrocell density point, system-level functions can now take advantage of the expanded logic density along with other ispMACH 5000MX device features: flexible on-chip memory, PLLs, sysI/O interface, and ispXP technology with instant-on capability that eliminates external PROM requirements.
The homogeneous ispXPLD architecture consists of a number of uniform multifunction blocks interconnected by a single-level, high-speed programmable global routing pool (GRP).
The GRP also connects the MFBs to the I/O cells.
Devices in the ispXPLD 5000MX family integrate from 8 to 32 MFBs into a single device.
Each MFB within an ispXPLD device can be programmed independently to implement 32 macrocells of SuperWide logic, an 8Kbit dual-port RAM, a 16Kbit single-port RAM or FIFO, or a 128 x 48bit content addressable memory.
Dedicated FIFO control logic is included on-chip so programmable resources are not consumed when providing these memory control functions.
While the basic logic block configuration supports up to 68 logic inputs in a single level of logic, cascading MFBs allow the devices to support functions of up to 136 inputs without incurring an additional level of logic delay, further raising the bar for a wide logic architecture.
Lattice's new ispXP technology enables its ispXPLD family (as well as its ispXPGA FPGA devices) to combine the programmability benefits found in both E2PROM-based nonvolatile PLDs as well as SRAM-based reconfigurable FPGAs.
As a result, the devices feature: "instant on" operation at system startup, allowing them to support critical system "heartbeat" functions without external initialisation; nonvolatile in-system programming, giving higher integration through the elimination of an external boot PROM; enhanced design security through the elimination of external programming bit streams; and infinite reconfigurability via an 8bit microprocessor port or JTAG boundary scan port for the ultimate in-system reprogrammability.
The ispXPLD 5000MX family is supported by Lattice's new ispLever v3.0 design tools.
The ispLever tools, Lattice's platform for next-generation logic design, provide designers with rapid access to the performance and features of the ispXPLD devices while maximising resource use.
This is achieved through timing driven placement and routing coupled with optimised synthesis support from vendors such as Mentor Graphics/Exemplar and Synplicity.
Additional third-party EDA tool support is provided through industry standard EDIF netlist import and export.
The ispLever software is available in PC as well as Unix workstation versions.
The ispLever design tools, including VHDL and Verilog synthesis tools, are available now for download from the Lattice website.
Production devices are available now for the ispXPLD 5256MX and ispXPLD 51024MX devices, along with the previously announced ispXPLD 5512MX, in both commercial (0 to 70C ambient) and industrial (-40 to +85C ambient) temperature grades.
The ispXPLD 5256MX devices are available in the 1.0mm ball pitch 256 fine pitch BGA package, and the ispXPLD 51024MX in 484 and 672 fpBGA packages.
Pricing for the ispXPLD 5256MX in volumes of 10,000 pieces starts at $9.50 and the ispXPLD 51024MX at $42.00.
The last member of the ispXPLD 5000MX family, the ispXPLD 5768MX, is scheduled for release later this year.
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