Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ORSPI4
Edited by the Electronicstalk Editorial
Team on 21 November 2003
ASIC and FPGA come together to optimise
SPI4.2
The ORSPI4 is a novel a field-programmable SPI4.2 SoC that efficiently integrates ASIC and FPGA technologies.
The ORSPI4 is a novel a field-programmable SPI4.2 SoC that efficiently integrates ASIC and FPGA technologies By combining the two approaches, Lattice has developed a more highly integrated, higher performance, lower cost and lower power SPI4.2 solution when compared to a full FPGA implementation
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The pre-engineered ASIC block on the ORSPI4 contains two SPI4.2 interface blocks, a high-speed quad datarate (QDR II) SRAM memory controller, four channels of 600Mbit/s to 3.7Gbit/s serdes, 8b/10b encoding/decoding and other supporting logic.
Connected to the ASIC block is a high performance FPGA with over 16,000 FPGA logic elements plus embedded block RAM.
The ORSPI4 FPSC is the world's most highly-integrated field programmable SoC targeted at line card applications for high-speed communications systems in the metro space.
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"The ORSPI4 FPSC is the tenth FPSC product that Lattice has introduced into the market, but the first targeted specifically at a growing line card segment", said Stan Kopec, Vice President of Corporate Marketing at Lattice.
"Analysts expect line card shipments to rise from 1.9 million ports in 2002 to 4.8 million ports in 2006, a 27% compound annual growth rate, and Lattice will be there with a highly integrated device that will bridge network processors, MACs and framers to high-speed serial backplanes", added Kopec.
SPI4.2 (System-Packet Interface, Level 4, Phase 2) is a recent system-level interface standard that enables the development of flexible, scalable systems for a converged data and telecommunications infrastructure.
Published in 2001 by the Optical Internetworking Forum (OIF), the SPI4.2 standard supports the transmission of multiple protocols at variable, high-speed data rates, including: packet-over-Sonet/SDH (POS), OC-192, Ethernet, Fast Ethernet, Gigabit Ethernet, 10 Gigabit Ethernet, and 10 Gigabit Fibre-Channel SAN.
SPI4.2 eliminates proprietary ASIC-based or specialised network processor interfaces traditionally used to support a broad range of data rates and services.
The benefits are a common standards-based interface facilitating inter-connection between diverse devices from multiple manufacturers.
Designed for packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and packet-over-Sonet/SDH (POS) applications.
SPI4.2 provides a common interface for 10Gbit/s wide area network (WAN), local area network (LAN), metro area network (MAN) and storage area network (SAN) technologies, and it is ideal for systems that aggregate low-datarate channels into a single 10Gbit/s uplink for long haul or backbone transmission.
Lattice's ORSPI4 FPSC is unique in the programmable market as it embeds the SPI4.2 core in precharacterised ASIC gates, unlike competitors who ship soft SPI4.2 IP cores which must be integrated into the overall design and face the uncertainties of FPGA place and route timing.
"Unlike other SPI4.2 implementations for FPGAs, the ORSPI4 FPSC embeds all the high-speed functions in an ASIC core of over 1 million gates, allowing the FPGA gates to be used for design-specific bridging functions", commented Stan Kopec, Vice President of Marketing at Lattice.
"Embedding these functions within a hard core assures performance, predictability and interoperability.
This implementation also provides a big advantage in terms of total power consumption.
Typical programmable-only FPGA IP cores consume upwards of 10W for one SPI4.2 interface implementation.
In comparison, the ORSPI4 dissipates only 3.1W per SPI4.2 implementation at 900Mbit/s operation.
This is a big advantage for power-hungry 10Gbit/s line cards", added Kopec.
"Line cards are getting 'smarter' all the time, with the incorporation of NPUs and traffic management capabilities.
This intelligence adds to board complexity with the potential for signal skew and strenuous layout constraints", added Kopec.
"The SPI4.2 spec defines a deskew technique that relies on a built-in training sequence with user-selectable repetition rate and duration.
Referred to as dynamic alignment, this timing mode eliminates phase errors due to PCB traces of unequal lengths by continuously monitoring the data and adjusting the phase of the clock to align with it.
This can be a challenging problem for programmable devices, but our FPSC technology affords us the opportunity to manage dynamic alignment with predictable and reliable ASIC technology", he concluded.
The SPI4.2 cores on the ORSPI4 FPSC provide dual 10Gbit/s Physical-to-Link Layer interfaces in conformance to the OIF-SPI4-02.0 specification.
Each block provides a bidirectional interface with an aggregate bandwidth of 14.4Gbit/s.
This is achieved by using 16 LVDS pairs each for transmit and receive channel operating at a data rate of 900Mbit/s with a 450MHz DDR clock.
Both static and dynamic alignment are supported at the receive interface.
DIP-4 and DIP-2 parity generation and checking are also supported.
8Kbyte of data buffering is provided by embedded dual-port RAM for both transmit and receive in each SPI-4.2 core.
Internal 1K deep main and shadow calendars supports scheduling of up to 256 ports.
The transmit and receive status FIFOs can also store flow control information for up to 256 ports, the maximum specified in the SPI-4.2 specification.
In order to provide wire-speed packet processing, the ORSPI4 also contains an independent memory controller block that provides data buffering between the FPGA logic and external memory and supports a throughput of greater than 20Gbit/s.
Data are transferred to and from memory through two sets of 36bit unidirectional data lines (one read, one write) operating at 200MHz DDR.
A set of 72 data signals is available to transfer data across the core-FPGA interface and allows the system to use the bandwidth available with second-generation QDR II SRAMs.
Of the 72 data signals, eight signals can be used either for parity or data.
A second memory controller can also be added in the FPGA section to provide two independent line-rate buffers if needed.
The high-speed serdes block supports four serial links, each operating at up to 3.7Gbit/s (2.96Gbit/s datarate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in receiver clock and data recovery (CDR) and transmitter pre-emphasis.
The serdes block is identical to that proven in Lattice's ORT82G5 and ORT42G5 FPSCs, supporting embedded 8b/10b encoding/decoding as well as link state machines for both 10Gbit/s Ethernet and Fibre Channel.
The state machines are IEEE P802.3ae/D4.01 XAUI compliant and also support FC (ANSI X3.230: 1994) link synchronisation.
The ORSPI4 FPSC also contains a dedicated microprocessor interface, a 32bit internal system bus (and 4bit parity), and built-in system registers that act as the control and status centre for the SPI4.2, serdes and memory controller blocks.
The FPGA portion of the device can also be configured through this interface.
The ORSPI4 FPSC in the 1036 fpSBGA (1mm ball pitch, thermally enhanced fine pitch ball grid array) package is currently shipping.
The unit price in quantities of 10,000 is $250.00.
The device will also be offered in an 1156 fpBGA package (1mm ball pitch, standard plastic fine pitch BGA) without the serdes channels.
The device is supported by Lattice's ispLever v3.1 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.
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