Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: ispMach 4256V
Edited by the Electronicstalk Editorial
Team on 18 February 2004
CPLD works as ideal AMD coprocessor
Bandspeed has selected the Lattice ispMach 4256V CPLD for use in its leading-edge 940K Gypsy Series wireless access point switch.
Bandspeed has selected the Lattice ispMach 4256V CPLD for use in its leading-edge 940K Gypsy Series wireless access point switch The 940K Gypsy Series is a next-generation Wi-Fi solution that employs spatial division multiple access (SDMA) sectorised switching in IEEE802.11a, b and g wireless LAN access points
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The Gypsy's unique design places the switching function in the access point while maintaining a form factor similar to conventional access points.
Targeted for high-density users and long-range applications, the Gypsy Series addresses the needs of customers who require increased coverage or bandwidth in their wireless environment.
"The choice of Lattice CPLDs was easy for Bandspeed.
Lattice ispMach CPLDs have the speed and low power that complement the AMD processor", said Blaine Kohl, Vice President of Marketing at Bandspeed.
"With the Gypsy, we are forwarding data in excess of 300Mbit/s, so our choice of processor and interface logic is deliberate and demanding.
Lattice's experience in CPLDs was a big factor in our selection", Kohl added.
"CPLDs remain a great value for leading-edge companies like Bandspeed that need fast time-to-market, excellent performance, and low power consumption", said Stan Kopec, Vice President of Marketing at Lattice.
"In the last two years, Lattice has diversified its product line with the addition of FPGAs, FPSCs, programmable mixed signal devices and high-speed serdes.
Nonetheless, leadership in CPLDs remains a key Lattice strength and is a source of great value for our customers", Kopec added.
At the heart of the Gypsy is an AMD Alchemy Au1500 processor that employs a MIPS32 architecture.
The Lattice ispMach 4256V CPLD interfaces with the processor to provide I/O expansion and support the processing of multiple radio channels.
This design provides the performance required to support custom applications such as Listen+Learn technology, which allows multiple Gypsy-enabled units to collaboratively select channelisation schemes by listening and learning from one another.
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