Programmable system chip meets basestation specs

Lattice Semiconductor and Tyco Electronics have successfully demonstrated a complete solution for the Open Base Station Architecture Initiative (OBSAI) Reference Point 3 (RP3) interface.

Lattice Semiconductor and Tyco Electronics have successfully demonstrated a complete solution for the Open Base Station Architecture Initiative (OBSAI) Reference Point 3 (RP3) interface.

The OBSAI architecture partitions the basestation into four modules: the RF module, the baseband module, the control and clock module and the transport block module.

The RP3 specification addresses the interface between the baseband and the RF modules using OBSAI-defined packets and a high-speed serial link.

The datarates on this link can run at either 768Mbit/s or 1.536Gbit/s, and the physical layer PCS must support 8b/10b encode/decode.

The RP3 interface defines a point to point serial interface for the transfer of data and control in a four layer protocol consisting of a physical layer for serialisation and coding of the data, a data link layer for message framing, a transport layer for routing and the application layer that provides mapping of the various packet types to the payload.

The Lattice/Tyco demonstration, given in conjunction with an OBSAI members meeting this week in Oxford, UK, is an integrated and complete solution.

It provides soft IP (intellectual property) implemented in FPGA gates to address data link layer functionality, while using the industry-leading embedded serdes and PCS core of the device to fulfil the physical layer requirements for the communication of RP3 packets over Tyco's unique backplane connector for slim slot spacing and/or high speed cable assembly.

"Lattice Semiconductor was one of the first semiconductor companies to become part of the OBSAI Alliance".

"The successful demonstration of this implementation of the OBSAI Reference Point 3 specification is a further step towards establishing the OBSAI specifications within the industry", said Jukka Klemettila, OBSAI Chairperson.

The target platform chosen by Lattice Semiconductor for the reference design was the ORT42G5, a field programmable system chip, or FPSC.

This device has sufficient FPGA gates to accommodate the soft IP portion of the design, while also providing physical layer functionality with its advanced embedded serdes and PCS capability.

The embedded ASIC technology supports very low power consumption of 225mW per channel, including the input-output buffers, and can accommodate both the 768Mbit/s and 1.536Gbit/s of the OBSAI specification by simply changing a register setting.

For ease of use, the device was mounted on a Lattice standard evaluation board.

Tyco Electronics, using either a 2mm HM 4+1 row connector with line card and backplane assembly, or a 1mm Giga I/O cable assembly, provided the physical interconnection channel.

Tyco's high-speed cable was used to transmit error-free data over a distance of 8m.

The backplane demonstration also showed data being transferred across an FR4-based test vehicle 1500cm long, assembled with 2mm HM 4+1 row (slim).

"Over the past few years Lattice Semiconductor and Tyco Electronics have established a close relationship", said Stan Kopec, Lattice Vice President of Corporate Marketing.

"The need to solve the problems associated with the error-free transmission of high-speed signals across backplanes and cable assemblies means that close co-operation between the electronics component vendors and connector suppliers is critical for success".

"The electrical properties of connectors and sockets, and their interaction with active components, have a significant effect on signal integrity, which is critical to system performance and must be considered in the early phase of any design".

Doron Lapidot, Director Circuit and Design, Tyco Electronics, Asia/Pacific and EMEA, said: "Tyco Electronics circuit and design engineers have characterised the total interconnect comprised of common FR4 material, 2mmHM 4+1 row (slim version) connectors and the Lattice ORT42G5 backplane FPSC as an active interconnect".

"The correlation between measured eye-pattern and simulated eye pattern was very close".

"Consequently, we've demonstrated the capability to predict signal integrity obstacles with greater than 95% accuracy, and rectify them before a system is built in order to achieve robust system interconnect performance at 1.536Gbit/s and beyond".

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