Product category:
Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever
Edited by the Electronicstalk Editorial
Team on 01 December 2004
Tool suite boasts faster FPGA design
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality.
The latest release of the ispLever programmable logic design tool suite offers a comprehensive upgrade and enhancement in performance and functionality FPGA Fmax performance has been increased by an average 22% and map, place and route runtimes have been reduced by 24% for a typical design, lessening the demand on computing resources
This article was originally published on Electronicstalk on 24 Apr 2002 at 8.00am (UK)
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The simple machine for complex design
"The simple machine for complex design" is the description given by Lattice Semiconductor to its next-generation ispLever design tools.
The simple machine for complex design
Dubbed "The simple machine for complex design", the latest generation of the ispLever design tool provides developers a simple powerful tool to use with all of Lattice's programmable logic products.
Enhancements include an I/O assistant for efficient placement of mixed I/O types, the addition of new power calculator and ispTracy logic analyser tools, a new project creation wizard, major upgrades in static timing analysis, floorplanning and DSP design, and a significantly faster and more fully featured ModelSim simulator from Mentor Graphics.
The ispLever design tools support all Lattice digital programmable logic devices, including the new LatticeECP-DSP (Economy Plus DSP) and LatticeEC (Economy) FPGA device families, and provide all the features required to develop a design from concept to programmed device.
"The ispLever 4.2 suite delivers unprecedented levels of performance, functionality, and ease-of-use to our customers", said Lattice Vice President of Software Chris Fanning.
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Programmable designs keep track of revisions
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite.
Approved cores speed programmable system design
The ispLeverCore Connection marks a new level of collaboration between Lattice and independent developers of intellectual property.
Upgrade for programmable logic design tools
The latest version of the ispLever design tool suite includes major upgrades in performance and features for the design of in-system programmable FPGA, CPLD and ispGDX devices.
"LatticeEC and LatticeECP-DSP performance has achieved industry leading standards for low-cost FPGA solutions, and the design suite's runtime and overall system performance have been substantially upgraded to further streamline FPGA design".
"These performance improvements, coupled with a multitude of new features and improved ease of use, make ispLever 4.2 a very powerful design tool suite", Fanning concluded.
The ispLever 4.2 design tools include the latest synthesis and simulation tools from industry leaders Mentor Graphics and Synplicity.
"Lattice continues to raise the bar for programmable logic tools by providing our customers the industry's most advanced synthesis and simulation tools as standard features and at no additional charge", said Stan Kopec, Lattice Vice President of Corporate Marketing.
"We work continuously with our partners to develop the highest level of design tool support for our new technologies, even as we refine the performance of our existing tools".
The Mentor Graphics Leonardo Spectrum synthesis product is standard and fully integrated into the ispLever 4.2 pushbutton design flow.
Further, the performance of the Mentor Graphics ModelSim 6.0 tool has significantly reduced simulation times, increasing productivity and improving design time to market.
"This release of Lattice's ispLever design tools includes the industry leading ModelSim and LeonardoSpectrum products, enabling powerful design flow and productivity benefits for customers targeting today's increasingly complex FPGA devices".
"Mentor Graphics and Lattice engineering teams collaborate closely to continue to drive that power and performance ever higher", said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics.
Lattice also plans to offer Mentor's Precision RTL synthesis tool to customers later this year.
The ispLever 4.2 tool suite also includes Synplicity's Synplify 7.7 as a standard feature.
"Synplify 7.7 includes several significant enhancements designed to boost the performance of Lattice silicon", said Joe Gianelli, Synplicity Vice President of Business Development.
"We've focused our efforts on the new LatticeECP-DSP and LatticeEC FPGA device families, and have achieved faster designs than ever before".
Design support is now available for the newest members of the LatticeECP-DSP and LatticeEC FPGA architectures, the LatticeECP6 and LatticeEC6.
The ispLever 4.2 tool suite also adds to the breadth of the ispLever blockset for Simulink functions targeting the LatticeECP-DSP architecture.
These blocks can be used to build DSP solutions in the Matlab/Simulink design environment, available separately from The MathWorks.
Design support for the LatticeECP/EC FPGAs has also been expanded to include the Lattice ispTracy logic analyser tool.
Using ispTracy, the designer can probe and analyse signal activity in the internal nodes of a physical FPGA during operation on a board.
The Lattice ispLever 4.2 tool suite includes many new tools and enhancements that make the design process more efficient and effective.
ispLever now allows the user to define the FPGA I/O structure and perform I/O design rule checking early in the design process, allowing the user to make critical I/O placement decisions prior to place and route activities.
This ability is particularly valuable for larger projects where design teams must define their I/O strategies for multiple modules early in the design process.
Creating a new ispLever design project is now a simple process.
The project wizard helps a user become productive quickly, and ensures that new design projects are initiated efficiently.
New Lattice-specific HDL design preference options are available in ispLever 4.2, providing users more alternatives to choose from to help them optimise their logic in Lattice FPGA architectures.
Design preferences, such as I/O assignments, can now be exported in a CSV (comma separated value) format for easy manipulation in spreadsheet programs.
This supports the easy transfer of FPGA design schematic models for use in printed circuit board design tools.
Lattice provides evaluation versions of all IP core netlists to help users quickly determine how a Lattice IP core can accelerate their design.
Now, these evaluation IP cores can be downloaded using a simple button in the ispLever Module/IP Manager tool.
Online help, error messaging and documentation have been significantly enhanced, making the design tools initially easier to learn and use as well as improving ongoing design efficiency and productivity.
The ispLever 4.2 design tools are available now in a variety of PC-, Unix- and Linux-based configurations.
The ispLever tools support all Lattice FPGA, FPSC, ispXPLD, CPLD, GDX and GAL products in an integrated, easy-to-use design platform.
List prices begin at $995.
Customers with current maintenance agreements will receive the ispLever 4.2 upgrade at no charge.
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