Product category:
Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever-Starter
Edited by the Electronicstalk Editorial
Team on 08 February 2005
Free tools to start on programmable
logic design
Lattice Semiconductor has released Version 4.2 of its web-downloadable ispLever-Starter programmable logic design tool suite.
Lattice Semiconductor has released Version 4.2 of its web-downloadable ispLever-Starter programmable logic design tool suite The ispLever-Starter tools are a complete programmable logic design environment supporting HDL design entry and management, synthesis, place and route, and on-chip debug for Lattice's newest, most popular programmable products
This article was originally published on Electronicstalk on 25 May 2005 at 8.00am (UK)
Related stories
Upgrade for free programmable logic software
The upgraded ispLever-Starter 5.0 design tools can now be downloaded from the Lattice website.
Big, fast and wide PLDs in full production
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family.
For the first time, the ispLever-Starter tools support selected members of Lattice's recently introduced high performance, low-cost LatticeEC FPGAs.
These tools provide a no-risk gateway for designers eager to create system-level solutions using this exciting new Lattice FPGA family.
The ispLever-Starter design tools are a complete programmable design tool solution intended for initial technology evaluation, students and other programmable logic users who require low- to medium-scale integration.
Further reading
Analogue front end is dynamically reconfigurable
Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.
Software programs analogue devices
Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
The tools are available for download from the Lattice Semiconductor website.
These tools are available as modules, so the user need only download the required portions of the software.
The ispLever-Starter Primary module contains the main ispLever engine, and includes design support for some of Lattice's newest and most popular CPLD products, such as the ispMACH 4000 families.
The optional LatticeEC Module includes the design tools and device libraries required to complete a design for the LatticeEC1 and EC3 FPGAs.
The LatticeEC1 is a 1.5K look-up table (LUT) FPGA with 18Kbit of embedded block RAM (EBR), two phase-locked loops (PLLs) and up to 112 I/O pins.
The LatticeEC3 device is a 3.1K LUT FPGA with 55Kbit of EBR, two PLLs and up to 160 I/O pins.
Five additional, larger members of the Lattice EC family ranging from 6.1K LUTs (LatticeEC6) to 32.8K LUTs (LatticeEC33) are currently available.
These devices, along with the LatticeEC1 and EC3, are supported by the Base and Advanced versions of Lattice's ispLever tools available for sale from Lattice distributors worldwide.
The ispLever-Starter ispXPGA module includes the design tools and device libraries required to complete a design for any Lattice ispXPGA nonvolatile FPGA device, from the 2K LUT LFX125 to the 15.4K LUT LFX1200.
A LeonardoSpectrum synthesis module enables the designer to target and synthesise HDL designs for Lattice programmable technologies using the LeonardoSpectrum synthesis tool from Mentor Graphics.
A Synplify synthesis module enables the designer to target and synthesise HDL designs for Lattice programmable technologies using the Synplify for Lattice synthesis tool from Synplicity.
A help and user guides module provides full support for for ispLever-Starter.
The ispLever 4.2 SP1 - Starter design tools are available now for download at no charge from the Lattice Semiconductor website.
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