Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeXP
Edited by the Electronicstalk Editorial
Team on 03 March 2005
Novel architecture cuts cost of
nonvolatile FPGAs
The new LatticeXP devices combine a low-cost FPGA architecture with nonvolatile, infinitely reconfigurable ispXP (expanded programmability) technology.
The new LatticeXP devices combine a low-cost FPGA architecture with nonvolatile, infinitely reconfigurable ispXP (expanded programmability) technology The LatticeXP devices deliver the benefits of instant-on operation, excellent security and a single-chip implementation and provide cost-effective alternatives to SRAM-based FPGAs and their associated boot memories
This article was originally published on Electronicstalk on 1 Jun 2005 at 8.00am (UK)
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IP cores are ready to run on latest FPGA family
Lattice Semiconductor has released a range of key ispLeverCore intellectual property (IP) modules for its recently announced LatticeXP FPGAs.
Software reconfigures FPGAs on the fly
New free programming software allows designers to reconfigure LatticeXP nonvolatile FPGAs in the field without interrupting system operation.
Through advanced 130nm Flash silicon technology, an optimised architecture and proprietary circuit design, die sizes of the new LatticeXP devices have been reduced over 80% compared with the previous generation of Lattice nonvolatile FPGAs.
First samples of the 10K look-up table (LUT) LatticeXP10 device are now available with the remaining four family members planned for second quarter availability.
"Lattice first delivered volume, nonvolatile FPGAs to the marketplace in 2003, and our customers responded positively", said Cyrus Tsui, Lattice Chairman and CEO.
Further reading
Microcontroller core is made for FPGA applications
The LatticeMico8 is an 8bit "soft" microcontroller core for the LatticeECP, LatticeEC and LatticeXP families of FPGAs, as well as the recently released MachXO family of crossover PLDs.
Nonvolatile FPGAs sleep on the job to save energy
Lattice Semiconductor has developed a novel power-saving feature that reduces standby power by over a factor of 1000 for its LatticeXP family of nonvolatile FPGAs.
Design services company chooses LatticeXP FPGA
Lattice Semiconductor has announced that design services firm Oztek has chosen the LatticeXP FPGA for use in several distinct designs.
"However, customers also told us that to expand their use of this 'ultimate' FPGA technology they required prices more consistent with that of SRAM-based FPGAs plus the associated boot PROMs".
"This new generation of LatticeXP products makes nonvolatility finally affordable for the growing number of users who prefer a nonvolatile solution".
"This unmet demand represents a large opportunity for Lattice that has not been addressed by the dominant FPGA market players".
LatticeXP devices are implemented on a cost effective, low-k, 130nm CMOS Flash process using copper metallisation.
The technology was codeveloped by Fujitsu and Lattice Semiconductor.
Production wafers are fabricated by Fujitsu in its state-of-the-art wafer fab.
The devices support operation from 1.2, 1.8, 2.5 or 3.3V power supplies.
The ispXP technology used in the LatticeXP devices combines SRAM and nonvolatile Flash memory to deliver an FPGA that is both nonvolatile and infinitely reconfigurable.
"Customers have told us that the concept of a nonvolatile, infinitely reconfigurable FPGA, with its associated one-chip solution benefits of instant-on operation and security, represents the FPGA 'promised land'", said Stan Kopec, Vice President of Marketing for Lattice.
"With such an FPGA, customers would have the best of both worlds: the infinite reconfigurability of SRAM and the many benefits of nonvolatility".
"Now the concept is reality", Kopec continued.
"We believe the LatticeXP will rapidly become the 'no compromise' FPGA for cost-conscious, high-volume applications".
The SRAM-based memory cells control the operation of the device logic and are loaded from the on-chip Flash memory in less than 1ms at power-up, providing instant-on capability, or boot up on user command.
The products can also be configured via a microprocessor interface, referred to as the sysConfig interface, or the JTAG interface.
Unlike traditional SRAM-based FPGAs, the LatticeXP device does not require an external boot memory and so provides a single-chip solution with the associated benefits of reduced board area and simplified system manufacture.
The absence of an external boot device also eliminates the need for an external bit-stream at boot up and the possibility of bit-stream snooping, a major security concern with SRAM FPGAs.
Security features prohibit bit-stream readback from the SRAM and Flash sections of the devices to further enhance security.
The LatticeXP architecture was developed concurrently, and from the "ground up", with that of the previously announced LatticeECP/LatticeEC FPGAs.
As with the low-cost LatticeECP/EC devices, all LatticeXP architectural elements such as logic blocks, I/O capabilities including DDR support and embedded memory, among others, were evaluated in the context of their targeted high-volume applications as the devices were defined.
The feature sets were then precisely sculpted to be neither excessive (driving up cost) nor "bare bones" (limiting the application range) in order to maximise their broad adoption.
The resulting combination of a superior streamlined architecture, compact circuit design and production-proven technology found in the LatticeXP devices allows them to provide the benefits of nonvolatile, infinitely reconfigurable FPGAs and to be cost-effective alternatives to SRAM-based FPGAs and their associated boot memories.
The LatticeXP devices will be offered in a range of five densities, from 3K to 20K LUTs.
The devices provide I/O counts from 62 to 340 in a variety of low-cost plastic quad flatpack (PQFP), thin quad flatpack (TQFP) and 1mm fine-pitch ball grid array (fpBGA) packaging.
The LatticeXP optimised architecture is.based on industry-standard, synthesis-friendly four-input look-up table (LUT) logic blocks.
A quarter of the logic blocks contain distributed memory, an optimisation that reduces cost while supporting the vast majority of application requirements for small amounts of distributed memory.
The availability of sysClock phase locked loops (PLLs) and embedded block RAMs (EBRs) allows designers to reduce costs further by integrating these functions within the FPGA, eliminating external discrete devices.
Advanced sysI/O buffer capability supports standards such as LVCMOS, LVDS, LVTTL and PCI, as well as SSTL and HSTL, allowing users to easily and efficiently interface to the industry's most popular bus standards.
These standards were carefully selected to maximise application range while minimising die area.
The LatticeXP devices have dedicated circuitry to simplify DDR memory interfaces, while providing the highest performance, integration, signal integrity and ease of design for FPGAs in this class.
DDR memory has become the low-cost memory of choice: estimates suggest DDR represented 75% of DRAM bits shipped in 2004, up from 39% in 2002.
In addition to a common FPGA architecture, the LatticeEC, LatticeECP and LatticeXP devices share a common design methodology and design tool flow supported by the Lattice ispLever design tool suite.
Lattice ispLever software provides designers with access, in one software package, to all Lattice digital devices and includes synthesis support using Mentor Graphics Precision RTL and Synplicity Synplify design tools.
The ispLever Version 4.2 Service Pack 1 provides initial LatticeXP support.
An extensive range of IP (intellectual property) cores, particularly suited for high-volume applications, will be available from both Lattice and its IP partners.
Complete details of IP support will be announced throughout 2005.
Samples of the first device, the 10K LUT LatticeXP10, are available now with the remainder of the family expected to sample during the first half of 2005.
These devices feature 216Kbit of embedded block RAM and either 188 (256 fpBGA) or 244 (388 fpBGA) general-purpose I/O pins.
The published price in 1000-off quantities for immediate shipment of the XP10 in the 256 fpBGA package is $32.95.
Volume prices (250,000 units) in 2006 are projected to be less than $15.
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