FPGA design delivers high-speed channel correction

Lattice Semiconductor has developed a Rake Receiver reference design, targeted at base stations in wireless telecomms applications.

Lattice Semiconductor has developed a Rake Receiver reference design, targeted at basestations in wireless telecomms applications.

A Rake Receiver is used to counter the effects of RF multipath fading due to atmospheric absorption, ionospheric reflection and refraction, and reflection from terrestrial objects such as mountains and buildings.

The technique uses several subreceivers, each delayed slightly, in order to tune in the individual multipath components and then combine them to optimise the signal reception.

The reference design uses the new LatticeECP (EConomy Plus) FPGAs that combine an optimised FPGA fabric with high-speed, dedicated DSP blocks on-chip.

"LatticeECP-DSP FPGAs are ideal for applications in which cost-effective DSP functionality is needed", said Stan Kopec, Lattice Vice President of Corporate Marketing.

"Our new Rake Receiver reference design is specifically designed to take advantage of the device family's embedded DSP support, delivering high-speed channel correction in a low-cost FPGA fabric".

"This W-CDMA solution is another example of Lattice 'bringing the best together' with unique silicon plus application expertise that gets our customers to market fast", Kopec added.

Lattice ispLever v4.2 design software supports the ECP family for design entry, simulation, and place and route.

In addition, the reference design includes a model of the Rake Receiver generated using The MathWorks Matlab.

The model supports data generation and simulation capabilities in the popular Matlab environment.

The reference design has the following features (one instance of the rake engine): 61.44MHz operating frequency; interpolation of 2x oversampled input data to one-sixteenth of a chip resolution; handles 16 control channels and 16 data fingers; simultaneous generation of 16 scrambling codes at chip rate; simultaneous generation of 16 orthogonal variable spreading factor (OVSF) codes; descrambling and dispreading of input signals with 16 different delays; channel correction (derotation and scaling) of descrambled and despread signals; combining of multiple descrambled, despread and channel-corrected signals from a variable number of fingers; independent early-late gate based symbol timing tracking based on each of 16 control channel signals; uses 18x18 multiply-accumulate DSP feature of LatticeECP FPGAs; time slicing hardware to support 16 rake fingers per "engine"; time slicing exploits distributed RAM capability (16 x 1bit per LUT) for the context switching between 16 fingers; uses a time-sliced "Farrow interpolator" to interpolate input data by a factor of eight.

The Rake Receiver reference design is available now for qualified Lattice customers.

A white paper and user guide for the reference design can be found on the Lattice website.

Source code for the design may be obtained free of charge through local Lattice sales offices.

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