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Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever 5.0
Edited by the Electronicstalk Editorial
Team on 06 May 2005
Programmable logic design tools upgraded
The latest version of the ispLever programmable logic design tool suite incorporates major additions and improvements to design flow and documentation.
Lattice Semiconductor has announced the immediate availability of its ispLever 5.0 programmable logic design tool suite Major additions and improvements to design flow and documentation make the ispLever features and point tools easy to learn and easy to use
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The ispLever tool suite is available in Windows, Unix and Linux versions.
"Our customers can unleash the power of Lattice programmable logic devices effectively and efficiently with a design system that is extraordinarily user friendly, offers exceptional functionality and performance and is now value priced at $695", said Stan Kopec, Lattice Vice President of Corporate Marketing.
Lattice Vice President of Software Chris Fanning said: "We've made ispLever 5.0 easier to learn and use than ever before, while adding many new and enhanced features and point tools".
"At the same time, our logic optimisation engine has been enhanced to give unprecedented performance and quality of results".
The ispLever 5.0 tool suite includes Synplicity's Synplify software for Lattice 8.0 synthesis.
This latest version of Synplify improves both speed and quality of results.
"Close collaboration over years of partnership with Lattice has now raised the bar for FPGA performance", said Andy Haines, Vice President of Marketing for Synplicity.
"The formidable combination of Synplify and ispLever software with the new Lattice FPGA silicon sets a new performance benchmark for the industry".
"We're excited about our recently expanded OEM agreement with Lattice, and look forward to delivering exceptional performance to our mutual customers for many years to come".
The ispLever 5.0 release marks the full integration and shipment of the Mentor Graphics Precision RTL synthesis and ModelSim simulation tools with the Lattice design tool suite.
"This development is especially important for FPGA designers because it is the first time that commercial, advanced versions of synthesis and simulation tools for complex FPGA design have been offered via any OEM offering to date", said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics.
"Through our agreement with Lattice, we have opened up the full breadth of Mentor's superior FPGA design flows and capabilities to our mutual customers, resulting in improved overall productivity and significantly lower silicon costs".
Significant additions and enhancements to documentation and tutorials make learning and mastering the ispLever design environment easier than ever.
Special emphasis has been placed on providing tutorials and examples throughout ispLever's design flow and point tools.
Learning resources have been comprehensively updated and integrated, including a new, faster help system with links to datasheets and resources on Lattice's website.
Top-level schematic design has been added to ispLever 5.0, which allows the user to create design function blocks and quickly visualise the entire design in a graphical representation.
This not only helps partition the design into manageable elements, but also simplifies the design review process.
Every point tool in ispLever 5.0 also has been enhanced.
The module/IP manager GUIs have been streamlined for better ease of use, and many new IP modules have been added for customers' designs.
Over 20 new DSP elements have been added to the ispLever DSP design library; the I/O assistant, which facilitates complex I/O assignment and rule checking, has been upgraded; significant enhancements have been made to the floorplanner to provide additional functionality, including multiple windows; the accuracy and flexibility of the power calculator have been enhanced; and the ispTracy logic analyser provides new cross-referencing, core integration facilities and optimised displays.
The ispLever 5.0 release marks a major advancement in the way ispLever tools are configured and licensed.
All customers now have access to design tools for all Lattice products, providing unmatched value to the user.
The downloadable ispLever-Starter configuration has also been expanded to include support for the entire LatticeEC FPGA family as well as added support for LatticeECP-DSP devices.
The ispLever 5.0 HDL-Base design tools for Windows, now supporting all Lattice programmable logic families and including ModelSim LE, Precision RTL Lattice Edition and Synplify 8.0, is list priced at $695 and is available immediately.
Unix and Linux versions are also available.
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